genesys zu 3eg Unable to run Debugger EDITR

[Jason3_14]

Hi,

I am following the steps from the following tutorial:

https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi

When I try to load the application with the debugger, I get the following error:

xsct% Info: Cortex-A53 #0 (target 9) Stopped at 0x0 (Cannot resume. Cannot read 'pc'. Cannot read 'r0'. Cortex-A53 #0: EDITR not ready)

I am using Vitis 2020.2 and Vivado 2020.2. There is no PL in the design. I have the PL-PS interface disabled. Its just a basic Hello World. 

The target is Genesys ZU 3eg  Rev. D I used both the board file and constraints file from the Digilent repository.

How do I load, run, and debug the application over JTAG?

 

regards,

Jason 

I think there might be a problem with the Block Automation in the Genesys Zu 3eg file. After running Block Automation the Address Editor is blank.

 

Edited December 8, 2021 by Jason3_14

[JColvin]

Hi @Jason3_14,

I am looking to replicate this in 2020.2; I will let you know what I find.

Thanks,
JColvin

[thinkthinkthink]

Are you running multiple Vitis instances at the same time ? I've had some issues on multiple boards where I would start a debugging session in Vitis while my board was already connected to another Vitis debbuging session and that would cause a lot of annoyances. 

Maybe make sure you Disconnect your debugging session before starting a new one.

[elodg]

Are you using the on-board USB/JTAG programmer?

Our current supported version is 2020.1. I have never experienced that error in the two versions we supported: 2019.1 and 2020.1. I would suggest a downgrade and try the hello world example we have: https://github.com/Digilent/Genesys-ZU/releases/tag/3EG%2FHELLO-WORLD%2F2020.1-1.

[Jason3_14]

Hi,

I tried the project zip from the repository with Vitis 2020.1
https://github.com/Digilent/Genesys-ZU/releases/tag/3EG%2FHELLO-WORLD%2F2020.1-1.

I get the same error. It looks like the debugger is downloading to the wrong location. Its starting at address 0. I rebooted my host machine before trying to connect and power cycled the Genesys.

[elodg]

16 hours ago, elodg said:

 

Are you using the on-board USB/JTAG programmer?

 

Are you using 2020.1?

 

[Jason3_14]

On 12/9/2021 at 12:09 PM, elodg said:

Are you using the on-board USB/JTAG programmer?

Our current supported version is 2020.1. I have never experienced that error in the two versions we supported: 2019.1 and 2020.1. I would suggest a downgrade and try the hello world example we have: https://github.com/Digilent/Genesys-ZU/releases/tag/3EG%2FHELLO-WORLD%2F2020.1-1.

I am using Vitis 2020.1 with the on-board USB/JTAG programmer. I just connect the USB cable directly to the board from the Host machine.

[elodg]

Would you please make sure when using 2020.1 that the "hw_server" process is also from 2020.1? Just make sure the process ends when closing a different version, so that launching in hardware from 2020.1 launches the proper hardware server.

Why do you say the download address is incorrect? If the application is linked to the DDR memory, offset 0x0 is the correct one.

Before the elf is downloaded the PSU needs to be initialized. Xilinx recommends the FSBL flow instead of the psu_init.tcl init flow . One advantage of the FSBL flow is that it supports dynamic DDR init. Our Reference Manual lists the different memories the Genesys ZU can be shipped with and links to the FSBL that should be used: https://github.com/Digilent/embeddedsw/tree/genesys-zu-20.1. Please download the embeddedsw repo, add it to Vitis (Xilinx -> Software Repositories -> Local), and generate a new ZynqMP FSBL application. Once built, you can try launching it in hardware by itself to verify you are not getting a launch error. If it goes well, you can add it to your application's launch configuration as the FSBL to use.

Watch the UART terminal for FSBL output.