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Found 2 results

  1. rob2018t

    Arty Z7 and Reset

    Hello fellow Digilent Members, I hope everyone is well. My Skill Level: I'm slowly progressing my knowledge of FPGA and Vivado using the Digilent Arty Z7-20 and Arty S7-50. Essentially quite a beginner and I've created simple RTL designs to flash LEDs, utilised the Microblaze, Zynq and made a AXI-4 IP block. All really exciting stuff IMO...I just need to make something more useful now. My Question: when designing with the Arty S7-50 I'm able to specify the board and then drag across the reset into my top diagram and/or utilise that when auto completing the design. However in the Arty Z7-20 design there is nothing listed like this in the board peripherals tab (is shows the switches, buttons, LEDs etc). Indeed there is nothing in the XDC constraints file either. I do see that my board is a Rev. B and that the board.xml is only for rev A.0 - I cannot find anything newer. Could someone please advise how to add the reset into my design please for the Arty Z7-20 ? I'm on different computers for the Vivado and my email access so sharing of screenshots or listings will be a little slow (not impossible though if it helps someone determine any issues). many thanks for any consideration :-)
  2. I have a question regarding the Nexys 4 DDR and his successor the Nexys A7: Will a working VHDL-Program, written for the Nexys 4 DDR XC7A100T-1CSG324C, work on an Nexys A7 XC7A100T-1CSG324C? (written in VHDL constructed in Vivado, using the constraint-file „Nexys-4-DDR-Master“ from your resource center [https://github.com/Digilent/digilent-xdc/] ) Is it possible to simply generate the Bitstream of this Program (made for the Nexys 4 DDR XC7A100T-1CSG324C) and download it onto the Nexys A7 XC7A100T-1CSG324C without making any changes to the code? Even if the Constraint-File for the Nexys-4-DDR-Master is used? The only difference in the Constraint-Files of the boards is the IOStandard for the Pmod Header JXADC, changed from LVDS to LVCMOS33. There shouldn‘t be any Problems since the voltage range of the previously used LVDS is within the range of the voltage for the LVCMOS33, right? Will a VHDL-Program that doesn‘t even use the Pmod Header JXADC work without problems? Or do I still have to alter something in my existing programm to make it work on a Nexys A7 XC7A100T-1CSG324C? Thanks in advance!
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