Min_ah Posted May 5, 2016 Share Posted May 5, 2016 Hello, I'm new to VHDL. I need to generate 500Hz from 50MHz clock frequency. I already got it. My problem here is how should the code to be adjusted if I want to change the duty cycle to 10%? Thank you. FreqDivider500Hz.vhd Link to comment Share on other sites More sharing options...
JColvin Posted May 5, 2016 Share Posted May 5, 2016 Hi Min_ah, I would recommend checking out these two threads here that talk about implementing PWM on an FPGA (links here and here). Let me know if you have any more questions. Thanks, JColvin Link to comment Share on other sites More sharing options...
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Min_ah
FreqDivider500Hz.vhd
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