After spending significant amount of time looking for solutions, I have managed to fit the design on to the board (the initial example is for a zybo z7-20) by turning off the Debug module on the MIPI CSI-2 receiver module. I have successfully exported the hardware and managed to run the provided C++ code. Even though I am able to communicate with the camera module via UART, I can not seem to acquire any video output from it. All I get is a static noise pattern, despite of trying to pick different options from the C++ menus. I am able to see the resolution change and read out the camera's registers (which seem to be correctly set according to the libraries), but that's it.
What could I possibly be doing incorrectly? I see the same pattern on a different monitor and have previously tested the hdmi output from the board both through plain VHDL and the IP integrator, via the test pattern generator. I do not see any errors apart from the negative slacks in Vivado, which is a known issue..
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makedestroyrepeat
Hello,
I have been trying for a while to run this PCAM example that is provided by Digilent on a Zybo z7-10 board:
https://github.com/Digilent/Zybo-Z7-20-pcam-5c/releases
After spending significant amount of time looking for solutions, I have managed to fit the design on to the board (the initial example is for a zybo z7-20) by turning off the Debug module on the MIPI CSI-2 receiver module. I have successfully exported the hardware and managed to run the provided C++ code. Even though I am able to communicate with the camera module via UART, I can not seem to acquire any video output from it. All I get is a static noise pattern, despite of trying to pick different options from the C++ menus. I am able to see the resolution change and read out the camera's registers (which seem to be correctly set according to the libraries), but that's it.
What could I possibly be doing incorrectly? I see the same pattern on a different monitor and have previously tested the hdmi output from the board both through plain VHDL and the IP integrator, via the test pattern generator. I do not see any errors apart from the negative slacks in Vivado, which is a known issue..
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