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Found 19 results

  1. Hello, I have been trying for a while to run this PCAM example that is provided by Digilent on a Zybo z7-10 board: https://github.com/Digilent/Zybo-Z7-20-pcam-5c/releases After spending significant amount of time looking for solutions, I have managed to fit the design on to the board (the initial example is for a zybo z7-20) by turning off the Debug module on the MIPI CSI-2 receiver module. I have successfully exported the hardware and managed to run the provided C++ code. Even though I am able to communicate with the camera module via UART, I can not seem to acquire any video output from it. All I get is a static noise pattern, despite of trying to pick different options from the C++ menus. I am able to see the resolution change and read out the camera's registers (which seem to be correctly set according to the libraries), but that's it. What could I possibly be doing incorrectly? I see the same pattern on a different monitor and have previously tested the hdmi output from the board both through plain VHDL and the IP integrator, via the test pattern generator. I do not see any errors apart from the negative slacks in Vivado, which is a known issue..
  2. I am frustrated with Vivado 2022.1 and was going to install the update to Vivado 2022.2 but that is 50GB download, and may not resolve the issues I'm having. Are there alternatives that allow the development in Verilog, and can create the bitstream to program a Zybo Z7-20?
  3. Hello, I'm trying to communicate between host (Windows PC) and device (Zybo Z7-20) with micro USB. I have followed the instructions through this link. However, while testing, when I connect the micro USB, 1. No power to Zybo: No recognition 2. Power to zybo: No recognition 3. Power, FPGA program through Xilinx SDK: Recognized as "USB Device" in drive. 4. Disconnect power and re-connect power: No recognition Further info on point 3: When the micro USB is recognized as USB device, it asks to format the drive every time with an error as "E:\ The directory name is invalid". Q1: I understand permission to format is a general procedure, but is it supposed to happen every time I plug in the micro USB? Q2: Isn't it supposed to be recognized as a removable device? When I open device manager, it is recognized under Disk drives as "Xilinx PS USB VirtDisk USB Device" rather than under Ports. Q3: After creating the BOOT.bin and loading into SD Card, JP5 has to be set on SD. Do I follow the same procedure to program after that? That is from Xilinx SDK -> Program FPGA -> Run As -> Launch on Hardware ? I'm a newbie to FPGAs altogether, so apologies if the questions are dim. Thanks in advance.
  4. Hello, I have just recieved my new board and jumped into the example tutorials using Vivado (2 hours to install) only to find when you get to launching the SDK that is is no longer there. Now you need Vitis (3 more hours install) but I am not finding much support in how to develop for a beginner. Can anyone point me to reasonable guides that are specific to the Zybo Z7? Thanks
  5. I have problems with HDMI demo on ZYBO Z7-20, The demo runs well but the resolutions are not correct its kind of crops the stream, the other problem is that on photos and videos red lines appear on edges of the objects and gradients, this happens on videos and photos and not on text, for example if I watch a youtube most of corners of objects get this red lines and other texts for example video description looks normal
  6. Hello friends, I'm trying to implement ov9281 camera on my zybo z7-20, I'm using pcam 5C demo project, so far i have achieved damaged frames from camera(included pictures) can someone help me understand what's wrong with it, why its damaged? btw I'm using digilent's mipi IPs and on pictures you can see the highlighted spots are flashlights shining on camera.
  7. Hi. I've tried to operate Pcam-5c at Zybo-Z7-zynq7020 using Xilinx Vivado tool. I refered to source code for Pcam-5c posted on github( https://github.com/Digilent/Zybo-Z7-20-pcam-5c/releases ). It operated successfully but I want to try again using other camera module instead of Pcam-5c. I have some problems in MIPI formatting data because Zybo7020 & Pcam-5c use RAW10 data but my camera module use RAW12 data. How can I use RAW12 format with Zybo-Z7-20 ?
  8. Hi, I have noticed an issue in a bare-metal application when polling the register XUARTPS_ISR (Channel Interrupt Status Register). No issues when I use XUART_SR (Channel Status Register) instead. The issue: When I poll XUART_ISR for TX_FULL and RX_EMPTY the UART interface becomes an unstable state. No sending and receiving after a few bytes is possible. Has somebody noticed the same issue or can somebody explain whats happening? Edit: My current code for the UART interface (Here I use XUARTPS_SR instead. But when I poll XUARTPS_ISR (0x14) it doesn't work.): #include <string.h> #include <dev/io.h> #define UART0_BASE 0xE0000000 #define UART1_BASE 0xE0001000 #define UART_CR_OFFSET 0x0 #define UART_CR_RXRST 0 #define UART_CR_TXRST 1 #define UART_CR_RXEN 2 #define UART_CR_RXDIS 3 #define UART_CR_TXEN 4 #define UART_CR_TXDIS 5 #define UART_MR_OFFSET 0x4 #define UART_IER_OFFSET 0x8 #define UART_BGEN_OFFSET 0x18 #define UART_SR_OFFSET 0x2C #define UART_SR_RXEMPT 1 #define UART_SR_RXFULL 2 #define UART_SR_TXEMPT 3 #define UART_SR_TXFULL 4 #define UART_FIFO_OFFSET 0x30 #define UART_BDIV_OFFSET 0x34 struct uart_reg { unsigned int cr; unsigned int mr; unsigned int ier; unsigned int bgen; unsigned int sr; unsigned int fifo; unsigned int bdiv; }; static struct uart_reg regs; void uart_init(void) { unsigned int tmp; regs.cr = (UART1_BASE + UART_CR_OFFSET); regs.mr = (UART1_BASE + UART_MR_OFFSET); regs.ier = (UART1_BASE + UART_IER_OFFSET); regs.bgen = (UART1_BASE + UART_BGEN_OFFSET); regs.sr = (UART1_BASE + UART_SR_OFFSET); regs.fifo = (UART1_BASE + UART_FIFO_OFFSET); regs.bdiv = (UART1_BASE + UART_BDIV_OFFSET); /* Check if RX/TX is enabled */ tmp = io_rd32(regs.cr); /* Skip init if RX/TX enabled */ if (tmp & ((1 << UART_CR_TXEN) | (1 << UART_CR_RXEN))) return; /* Reset RX/TX paths */ tmp = io_rd32(regs.cr); tmp |= ((1 << UART_CR_TXRST) | (1 << UART_CR_RXRST)); io_wr32(regs.cr, tmp); do tmp = io_rd32(regs.cr); while (tmp & ((1 << UART_CR_TXRST) | (1 << UART_CR_RXRST))); /* Set baudrate to 115200; UART Reference Clock: 100MHz */ io_wr32(regs.bgen, 124); io_wr32(regs.bdiv, 6); /* Set mode: 8 Databit, 1 Stopbit, No Parity */ io_wr32(regs.mr, 0x20); /* Enable RX/TX */ tmp = io_rd32(regs.cr); tmp &= ~((1 << UART_CR_TXEN) | (1 << UART_CR_RXEN)); io_wr32(regs.cr, tmp); } int uart_send(unsigned char *buf, int len) { int i; unsigned int tmp; for (i = 0; i < len; i++) { do tmp = io_rd32(regs.sr); while (tmp & (1 << UART_SR_TXFULL)); io_wr08(regs.fifo, buf[i]); } return len; } int uart_recv(unsigned char *buf, int len) { int i; int ret = 0; unsigned int tmp; tmp = io_rd32(regs.sr); if (tmp & (1 << UART_SR_RXEMPT)) return 0; for (i = 0; i < len; i++) { buf[i] = io_rd08(regs.fifo); ret++; tmp = io_rd32(regs.sr); if (tmp & (1 << UART_SR_RXEMPT)) return ret; } return ret; }
  9. Hi. I have a problem while trying lwIP Echo server wiht Zybo-Z7 I follow this tutorial faithfully https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start but I face with a problem This problem occurs for both connection through router and connection directly with my laptop or desktop I try with 3 PC and all of it shows same result. Google suggest me to configure ethernet to be 100Mbps half duplex with Fixed IP settings and it doesn't work. I double-check that I'm using correct MIO pin and fix the 100Mbps at SDK. Is there any solution to resolve this problem? Thank you.
  10. in the Zybo-Z7 P-CAM 5c Demo that is from https://github.com/Digilent/Zybo-Z7-20-pcam-5c?_ga=2.84117977.1367158795.1590938145-1282991817.1586099508 , it uses axi video stream which only contain component below in the axi_video stream bus : axis_video_tready axis_video_tuser axis_video_tvalid axis_video_tdata axis_video_tlast in my case i want to make a video processing using vivado hls after making the IP block of my vidio processing the ip generated with ontain component below in the axi_video stream bus : axis_video_tready axis_video_tuser axis_video_tvalid axis_video_tdata axis_video_tlast axis_vidoe_tstrb axis_video_tdst axis_video_tkeep axis_video_tid after making the ip and conneting to zybo Z7 Pcam 5c demo i couldn't see the output of the camera anymore hopefully any one can help my problem to match or create an axi video stream in vivado hls for project zybo-z7 Pcam 5c demo
  11. Hello, I'm new to this form, looking for some help with the Dual H bridge PMOD DHB1. I connected my power supplier to J4, my motors to J5 and J6. I have a custom IP that uses switches to drive motor speed with most significant bits of a duty cycle for PWM output at 2kz. I also have 2 switches connected to the DIR1 and DIR2 respectively. I also have button 3 connected to a reset condition to initialize code, inputs and outputs. To help debug, I connected the EN1 and EN2 output of the custom IP to the board LEDs to confirm that the signals are working correctly. I also checked the voltage at EN1 and appears to be doing what I expect. However, I do not have any motor actuation. I checked the voltage at the J4 = 8V, but neither J5 or J6 have any voltage differential between M+ and M-. I checked the sleep and fault pins they are both high, which is normal behavior as they are pulled low when in sleep or faulted state. Any advice on what I can do to find an issue would be appreciated. Thanks, Dave HBridgeTOP Hbridgecode (1)
  12. I am newbie with ZYBO Z7-20 working on hdmi in demo , i have done as shown on github digilent project page in VIVADO 2019.1 , But unable to get the video output ,but my system detecting the Board as DGL 720P CEA and UART port shows HDMI UNPLUGGED i have tried hdmi pass through , My system is not detecting the display itself i see video capture .state is video disconned in VIdeoinitilaztion it not changed any where ..and video_start function wont work Please Help ... Whether i have to change vivado version or any code
  13. Hello, I'm working with the Zybo Pcam 5C (18.2) reference design. While using the default resolution of 1920 * 1080 - I observe the AXI Stream but exiting from the GAMA CORRECTION IP (this is last core in the video chain before the VDMA). A strange thing I noticed is that the first 4 lines at the beginning of each frame are a constant 0xAE for all pixels. ( all the red , green and blue pixels have the same value which is 0xAE ). After the first 1920 * 4 pixels non - constant data starts to arrive. Why is this ? Is this the way the sensor outputs data ?
  14. Hello to everybody! I'm built custom Embedded Linux distro which based on Digilent Base-Linux FPGA design (https://github.com/Digilent/Zybo-Z7-20-base-linux) with help Xilinx Petalinux env. In this design was implemented XADC support. From the default BSP package from Digilent repository, I added support XADC to the device tree. How I can test this implementation from a working Linux image. I need to write a driver or I already can work with XADC?
  15. Hello, We are trying to generate the SPI protocols signals from the Zybo-Z710 board, which uses Zynq-7000 SoC. Since, the PS section of the chip contains two SPI modules. Can anyone tells me the procedure for activating the SPI line inside the PS. I want to use this SPI lines to transfer data and provide control to the another module. Thanks AMOL
  16. I have implemented a small system with ZYBO-Z7 20 , It will send the switch status through Ethernet interface . Implemented with AXI GPIO and LWIP ,UNICAST ,BOARD HAS CONSTANT IP and REMOTE IP is CONSTANT. i am not using DNS I am able to Send packets if Board is connected directly to LAPTOP and i am able to PING the Board from LAPTOP But when the Same setup when connected to Switch [allied telesis] i am not able ping the board and no packets are flowing ... Can any one help me where i have to look...
  17. Hello, I am working on the Zybo-Z7-10 development board, I want to establish a web server application to upload files from my PC and send it to web browser by HTTP POST and extract data inside the file, I am using the lwIP stack and downloaded the xapp1026 files from the gitHub, right now I can run the example application correctly, but I want to change the content inside the image.mfs file provided by the xilinx, I cannot open it, once I open the image.mfs by NotePad, unreadable characters are displayed, I found that at the top of this file, there is a css part, on the bottom of this file I can recognize that there is a html part, so I have modified it by adding a part of <input type= "file".....> , however it is vulnerable to errors, besides, i still need to write the js functions for getting the file. Do you know how can I create my own web browser and do not use the image.mfs file? Actually, I tried the mfsgen -cvbf command too, but I cannot change anything inside the file! can you help me on this problem or provide me with some references for the same question? Thanks a lot!
  18. Trying to get started with the Zybo-Z7 board and following the "Getting Started with Zynq" tutorial ( here ). Using Vivado 2018.2 because that's what the latest Pcam tutorial uses (my ultimate application). I can get down to the point where you add the 2 gpio IP blocks. But when "Run Connection Automation" is selected, the popup window does not have an option to select the board interface (switches and LEDs). These are un-commented in the constraint file. I'm using the latest board files and constraint files. Project Summary shows the correct board part. I have a feeling I'm missing something simple. I've uninstalled/reinstalled everything. It's a fairly new W10 computer. I've looked at several other getting started type tutorials and no clues there. I've done embedded systems before so not a complete novice, but i feel like one right now...
  19. Can anyone suggest me how to program the UART/USB available in the ZYBO Z7 board and use it as a port to feed the data from the PC/SERVER ?