I am trying to run the xilinx example project xemacps_example_intr_dma (example) on baremetal zynq. I have tried copy pasting requisite files into a project and having it build by importing the example through the .mss file of the bsp. The hardware export is from a slightly modified version of the digilent getting started example using the master xdc file.
The project compiles and loads but never enters the interrupt handler and gets hung at the while(!FramesRx) at line 819. My block diagram has a fixed io pin from the zynq ps running over to an external interface pin labeled fixed io which includes a subfield labeled mio. However the graphical ip-reconfig utility of the zynq ps has enet0 selected and the MIO configuration tab shows the MIO pins as 16..27 which I think are the correct pins for the enet PHY.
A few questions come to mind:
Presumably the phy chip has some specific configuration that has to occur that may not be a part of the rgmii specification, however the xilinx example makes no reference to configuring a board specific phy. I am missing this step and I need to write code to perform some config-init function specific to this chip? A brief look at the realtek phy however seems to show most options are configured using pull down resistors...
Secondly, does the constraints file need to specify something about the ethernet pins? Because I find no mention of them in the master.xdc file but I also see no mention of the uart pins and the uart(through usb-to-uart chip) runs fine.
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SuMatt
I am trying to run the xilinx example project xemacps_example_intr_dma (example) on baremetal zynq. I have tried copy pasting requisite files into a project and having it build by importing the example through the .mss file of the bsp. The hardware export is from a slightly modified version of the digilent getting started example using the master xdc file.
The project compiles and loads but never enters the interrupt handler and gets hung at the while(!FramesRx) at line 819. My block diagram has a fixed io pin from the zynq ps running over to an external interface pin labeled fixed io which includes a subfield labeled mio. However the graphical ip-reconfig utility of the zynq ps has enet0 selected and the MIO configuration tab shows the MIO pins as 16..27 which I think are the correct pins for the enet PHY.
A few questions come to mind:
Presumably the phy chip has some specific configuration that has to occur that may not be a part of the rgmii specification, however the xilinx example makes no reference to configuring a board specific phy. I am missing this step and I need to write code to perform some config-init function specific to this chip? A brief look at the realtek phy however seems to show most options are configured using pull down resistors...
Secondly, does the constraints file need to specify something about the ethernet pins? Because I find no mention of them in the master.xdc file but I also see no mention of the uart pins and the uart(through usb-to-uart chip) runs fine.
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