I've opened the Cora-Z7-10-base-linux project in Vivado 2017.4 (to avoid any version-dependent issues) on Linux, and I was hoping to be able to route the UART 1 device from the ZYNQ7 Processing System out to the outside world. Ideally I'd like it to be wired up to the DP0 and DP1 pins, as I have a nice little Arduino Click2 adapter that I can put an RS485 Click board one.
However, being very new to all this Zynq/Cora/Vivado stuff, I'm not sure how to do it.
I started off (with a bit of advice from someone who knows more about this than me, but was rushing off home!) by opening the ZYNQ7 Processing System for re-customisation, and, in the Peripheral I/O Pins view, clicking on the EMIO button at the end of the UART1 row, and clicking OK. At this point, the block design is updated and UART_1 shows up on the ZYNQ7 Processing System block. Then I expanded UART_1 and, for each of the signals, right clicked and selected "Make external" before saving the block design and doing "Generate Block Design" again. The signal names related to UART 1 then showed up in the wrapper VHDL.
Next, to try to map then to the Arduino I/O pins, I edited the constraints file by uncommenting and updating the ck_io0 and ck_io1 lines to be as follows:
Question
jmccabe
Hi,
I've opened the Cora-Z7-10-base-linux project in Vivado 2017.4 (to avoid any version-dependent issues) on Linux, and I was hoping to be able to route the UART 1 device from the ZYNQ7 Processing System out to the outside world. Ideally I'd like it to be wired up to the DP0 and DP1 pins, as I have a nice little Arduino Click2 adapter that I can put an RS485 Click board one.
However, being very new to all this Zynq/Cora/Vivado stuff, I'm not sure how to do it.
I started off (with a bit of advice from someone who knows more about this than me, but was rushing off home!) by opening the ZYNQ7 Processing System for re-customisation, and, in the Peripheral I/O Pins view, clicking on the EMIO button at the end of the UART1 row, and clicking OK. At this point, the block design is updated and UART_1 shows up on the ZYNQ7 Processing System block. Then I expanded UART_1 and, for each of the signals, right clicked and selected "Make external" before saving the block design and doing "Generate Block Design" again. The signal names related to UART 1 then showed up in the wrapper VHDL.
Next, to try to map then to the Arduino I/O pins, I edited the constraints file by uncommenting and updating the ck_io0 and ck_io1 lines to be as follows:
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { UART1_RX_0 }]; #IO_L11P_T1_SRCC_34 Sch=ck_io[0] set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { UART1_TX_0 }]; #IO_L3N_T0_DQS_34 Sch=ck_io[1]Save, and "Generate Bitstream" to make all the steps run..
Unfortunately it breaks here with the following errors and critical warnings in the Messages view:
Implementation Design Initialization [Vivado 12-1411] Cannot set LOC property of ports, Cannot set PACKAGE_PIN property of ports, port UART1_RX_0 can not be placed on PACKAGE_PIN U14 because the PACKAGE_PIN is occupied by port shield_dp0_dp13_tri_io[0] ["/home/jmccabe/work/Cora-Z7-10/Cora-Z7-10-base-linux/src/constraints/Cora-Z7-10-Master.xdc":92] Place Design [Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0). The following are banks with available pins: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1 has only 0 sites available on device, but needs 1 sites. Term: UART1_RX_0 [Place 30-374] IO placer failed to find a solution Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | IO Placement : Bank Stats | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | 0 | 0 | 0 | | | | | | | | 13 | 0 | 0 | | | | | | | | 34 | 50 | 33 | LVCMOS33(33) | | | +3.30 | YES | | | 35 | 50 | 41 | LVCMOS33(41) | | | +3.30 | YES | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | | 100 | 74 | | | | | | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ IO Placement: +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | BankId | Terminal | Standard | Site | Pin | Attributes | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 34 | Shield_I2C_scl_io | LVCMOS33 | IOB_X0Y1 | P16 | | | | Shield_I2C_sda_io | LVCMOS33 | IOB_X0Y2 | P15 | | | | Shield_SPI_io0_io | LVCMOS33 | IOB_X0Y29 | W15 | | | | Shield_SPI_io1_io | LVCMOS33 | IOB_X0Y46 | T12 | | | | d_dp0_dp13_tri_io[0] | LVCMOS33 | IOB_X0Y28 | U14 | | | | _dp0_dp13_tri_io[10] | LVCMOS33 | IOB_X0Y27 | U15 | | | | d_dp0_dp13_tri_io[1] | LVCMOS33 | IOB_X0Y43 | V13 | | | | d_dp0_dp13_tri_io[2] | LVCMOS33 | IOB_X0Y40 | T14 | | | | d_dp0_dp13_tri_io[3] | LVCMOS33 | IOB_X0Y39 | T15 | | | | d_dp0_dp13_tri_io[4] | LVCMOS33 | IOB_X0Y8 | V17 | | | | d_dp0_dp13_tri_io[5] | LVCMOS33 | IOB_X0Y7 | V18 | | | | d_dp0_dp13_tri_io[6] | LVCMOS33 | IOB_X0Y11 | R17 | * | | | d_dp0_dp13_tri_io[7] | LVCMOS33 | IOB_X0Y37 | R14 | * | | | d_dp0_dp13_tri_io[8] | LVCMOS33 | IOB_X0Y24 | N18 | | | | _dp26_dp41_tri_io[0] | LVCMOS33 | IOB_X0Y12 | R16 | | | | _dp26_dp41_tri_io[1] | LVCMOS33 | IOB_X0Y45 | U12 | | | | _dp26_dp41_tri_io[2] | LVCMOS33 | IOB_X0Y44 | U13 | | | | _dp26_dp41_tri_io[3] | LVCMOS33 | IOB_X0Y30 | V15 | | | | _dp26_dp41_tri_io[4] | LVCMOS33 | IOB_X0Y32 | T16 | | | | _dp26_dp41_tri_io[5] | LVCMOS33 | IOB_X0Y31 | U17 | | | | _dp26_dp41_tri_io[6] | LVCMOS33 | IOB_X0Y10 | T17 | | | | _dp26_dp41_tri_io[7] | LVCMOS33 | IOB_X0Y9 | R18 | | | | _dp26_dp41_tri_io[8] | LVCMOS33 | IOB_X0Y3 | P18 | | | | _dp26_dp41_tri_io[9] | LVCMOS33 | IOB_X0Y4 | N17 | | | | user_dio_tri_io[10] | LVCMOS33 | IOB_X0Y17 | W20 | | | | user_dio_tri_io[2] | LVCMOS33 | IOB_X0Y22 | N20 | | | | user_dio_tri_io[3] | LVCMOS33 | IOB_X0Y21 | P20 | | | | user_dio_tri_io[4] | LVCMOS33 | IOB_X0Y23 | P19 | | | | user_dio_tri_io[5] | LVCMOS33 | IOB_X0Y49 | R19 | | | | user_dio_tri_io[6] | LVCMOS33 | IOB_X0Y20 | T20 | | | | user_dio_tri_io[7] | LVCMOS33 | IOB_X0Y0 | T19 | | | | user_dio_tri_io[8] | LVCMOS33 | IOB_X0Y19 | U20 | | | | user_dio_tri_io[9] | LVCMOS33 | IOB_X0Y18 | V20 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 35 | Shield_SPI_sck_io | LVCMOS33 | IOB_X0Y62 | H15 | | | | Shield_SPI_ss_io | LVCMOS33 | IOB_X0Y88 | F16 | | | | btns_2bits_tri_i[0] | LVCMOS33 | IOB_X0Y91 | D20 | | | | btns_2bits_tri_i[1] | LVCMOS33 | IOB_X0Y92 | D19 | | | | rgb_led[0] | LVCMOS33 | IOB_X0Y55 | L15 | | | | rgb_led[1] | LVCMOS33 | IOB_X0Y68 | G17 | | | | rgb_led[2] | LVCMOS33 | IOB_X0Y58 | N15 | | | | rgb_led[3] | LVCMOS33 | IOB_X0Y99 | G14 | | | | rgb_led[4] | LVCMOS33 | IOB_X0Y56 | L14 | | | | rgb_led[5] | LVCMOS33 | IOB_X0Y53 | M15 | | | | _dp0_dp13_tri_io[11] | LVCMOS33 | IOB_X0Y75 | K18 | | | | _dp0_dp13_tri_io[12] | LVCMOS33 | IOB_X0Y72 | J18 | | | | _dp0_dp13_tri_io[13] | LVCMOS33 | IOB_X0Y61 | G15 | * | | | d_dp0_dp13_tri_io[9] | LVCMOS33 | IOB_X0Y83 | M18 | | | | dp26_dp41_tri_io[10] | LVCMOS33 | IOB_X0Y84 | M17 | | | | dp26_dp41_tri_io[11] | LVCMOS33 | IOB_X0Y77 | L17 | | | | dp26_dp41_tri_io[12] | LVCMOS33 | IOB_X0Y73 | H17 | | | | dp26_dp41_tri_io[13] | LVCMOS33 | IOB_X0Y71 | H18 | | | | dp26_dp41_tri_io[14] | LVCMOS33 | IOB_X0Y67 | G18 | | | | dp26_dp41_tri_io[15] | LVCMOS33 | IOB_X0Y81 | L20 | | | | user_dio_tri_io[0] | LVCMOS33 | IOB_X0Y82 | L19 | | | | user_dio_tri_io[11] | LVCMOS33 | IOB_X0Y80 | K19 | | | | user_dio_tri_io[1] | LVCMOS33 | IOB_X0Y86 | M19 | | | | vaux0_v_n | LVCMOS33 | IOB_X0Y97 | B20 | | | | vaux0_v_p | LVCMOS33 | IOB_X0Y98 | C20 | | | | vaux12_v_n | LVCMOS33 | IOB_X0Y69 | F20 | | | | vaux12_v_p | LVCMOS33 | IOB_X0Y70 | F19 | | | | vaux13_v_n | LVCMOS33 | IOB_X0Y63 | G20 | | | | vaux13_v_p | LVCMOS33 | IOB_X0Y64 | G19 | | | | vaux15_v_n | LVCMOS33 | IOB_X0Y51 | J16 | | | | vaux15_v_p | LVCMOS33 | IOB_X0Y52 | K16 | | | | vaux1_v_n | LVCMOS33 | IOB_X0Y93 | D18 | | | | vaux1_v_p | LVCMOS33 | IOB_X0Y94 | E17 | | | | vaux5_v_n | LVCMOS33 | IOB_X0Y65 | H20 | | | | vaux5_v_p | LVCMOS33 | IOB_X0Y66 | J20 | | | | vaux6_v_n | LVCMOS33 | IOB_X0Y59 | J14 | | | | vaux6_v_p | LVCMOS33 | IOB_X0Y60 | K14 | | | | vaux8_v_n | LVCMOS33 | IOB_X0Y95 | A20 | | | | vaux8_v_p | LVCMOS33 | IOB_X0Y96 | B19 | | | | vaux9_v_n | LVCMOS33 | IOB_X0Y89 | E19 | | | | vaux9_v_p | LVCMOS33 | IOB_X0Y90 | E18 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. [Common 17-69] Command failed: Placer could not place all instancesIt seems that I naively thought that those lines being commented out meant those signals weren't connected (shows how little I know!).
Can anyone give me any pointers on how to overcome this, or how I should be doing this?
Any help will be very gratefully appreciated.
John
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