Arty Basic design with microBlaze - Vivado asks for the Inout and Output delays constraints for the Uart's Rx and Tx - Do not know how to create them

[jcv65]

Hi,

I am implementing in Vivado the Arty's Microblaze based design that Adam Taylor posted on his website: http://adiuvoengineering.com/?p=626I

I am having problems with it:

Synthesis ran without any high importance warnings, but at the end of implementation I get three high severity warnings after I run the "Report Timing Summary":

• USB_UART_RXD:  Port with no Input Delay
• USB_UART_TXD:  Port with no Input Delay
• ddr3_sdram_reset_n: Port with no Output Delay

I do not know how should I constrain these inputs and outputs.

(Note: My Arty environment is working ok (board files have been downloaded and installed).  I already have ran some basic logic circuits in the ARTY board successfully.  My problems started with this project that includes the Microblaze and the uart)

Attached are the snapshot of my block design (It is basically a copy of Adam Taylor's design) and a copy of the warnings I get.

Let me know if I need to do something about these warnings, and if so, how,

Thanks!

 

[ASICs]

Hi,

Generally if I don't have the outputs consumed by another device I don't worry about the warnings, however, Xilinx recommends that ALL I/O be constrained to make sure that the tool doesn't work too hard in the wrong area when implementing the timing closure. That said, you might want to take a look at this Xilinx quick take video : https://www.youtube.com/watch?v=hX7LpZlSmyo if you do not know how to constrain outputs in an XDC file (<top_level>.xdc).

I hope this helps,

Paul