JColvin

Hi @acarrou,
I reached out to Digilent's Test and Measurement Product Manager and received the following response:
Thank you,
JColvin

Hello guys,
 
my name is Mischa and I work as a scientific assistant at the University of Applied Sciences in Mannheim, Germany. I am using the Analog Discovery 2 with the impedance analyzer module for impedance measurement of roller bearings under different conditions (load, speed, lubricant) aswell as in single tribological contacts.
I am very happy to have found these forums with a lot of helpful information from the staff and members and I am looking forward to work with you.
 

Hi @hola,
I'd like to offer some words of caution regarding your goal of transmitting wireless data with the Pmod WiFi. I will start by saying that yes it is technically possible to do what you want, but there are a few things to consider.
- The 54 Mbps listed on the Pmod WiFi is the theoretical maximum rate available through WiFi 2 networks (previously known as 802.11g). These rates, quoted from Microchip's datasheet, are really only obtainable in specialized lab setups. The speed you will get will be much lower than that due to latency, overhead associated with the software stacks, and general quality and traffic on the actual WiFi network you will connect to. Because of this, I don't have a real-world transfer rate to quote for you, but I would also not be putting all of my expectations that the 30 Mbps will for sure be achieved.
- "My first question at this point is that can I just follow the steps explained in the youtube video even with VC707 board which is not your product." You would not be able to use these steps directly, no. A number of the steps used various board file materials from Digilent to help enable the connections. You might be able to download Digilent's vivado-library, https://github.com/Digilent/vivado-library, and just add the Pmod WiFi IP to your block design and get the appropriate AXI and MicroBlaze connections made, but I don't know what other nuances might be associated with that.
- "My second question is that could I communication data through FPGA board and Pmod wifi by using SPI communication?" All protocol and associated WiFi stack materials are available in the documentation and driver/src materials for the Pmod WiFi: https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodWIFI_v1_0. The demo that is closest to what you are describing would be the HTTPServer demo where you are able to set and view the status of different IOs on the FPGA through a locally hosted .html page. It does not offer streaming of data so to speak, though the echo server/client demos could probably be adjusted on both the board and host computer application side to change this behavior.
- Since you are new to this field and will probably want to be doing a lot of proof of concept and other development work (though I don't know your system constraints or budget) I would probably recommend getting a lower cost board than the VC707 to get some development testing done. You can also do a lot of development work in Vivado and SDK/Vitis directly without any hardware to make sure all of the board designs and applications are able to build correctly if you wish.
Thanks,
JColvin

Welcome @rehsd!

Hi @Durba Chatterjee,
The Cora Z7 does not have a way to measure current usage internally like the ZC702 or the Zybo Z7 boards. There is a PMIC on the board, but looking through it's datasheet, https://www.dialog-semiconductor.com/products/soc-processor-pmics/da9062#tab-field_tab_content_resources, I don't believe you would be able to directly get the current usage from that IC anyways.
Xilinx does have a Power Estimator tool, https://www.xilinx.com/products/technology/power/xpe.html, that can give you some good details on power usage, but Digilent does not have any guides on using this tool.
Thanks,
JColvin

Hello,
I am working on recreating the Pmod WiFi setup with an Arty A7 35.
Thanks,
JColvin

Hi @Kenechukwu Aniagboso,
I've merged your new post with your original one.
I have not re-created the circuit you made, but I suspect the issue you are encountering is in these two lines:
That end of capacitor should not be connected to ground; it instead should be connected to the voltage input (W2 based on what you selected) and the oscilloscope lead of interest (2+). The connection to ground is "behind" those connections, and is already taken care of within the Analog Discovery 2 hardware itself.
Thanks,
JColvin

Hello @afif.ramadhan,
I have reached out for some more feedback from another engineer more familiar with the Zmod IPs about this.
Thank you,
JColvin

I just completed my first mini-project on my new Arty A7 (my first FPGA). ? On Windows 11 with Vitis/Vivado 2021.2, I have the OLEDrgb working. It's unlikely I did everything the best or most proper way, but it's working. If anyone is interested, I shared a walkthrough with all of the steps I took to get the OLEDrgb working on my A7.
Arty A7 & OLEDrgb Pmod Walkthrough
All suggestions on how to improve the implementation are welcome. I can update the instructions with any recommendations you may have. Thanks!

Hi @Kenechukwu Aniagboso,
This looks like a homework assignment to me, but the answer of where to connect the Analog Discovery 2 pins to measure the voltage in and voltage out points are directly in your schematic.
In terms of the actual physical connectivity since it sounds like this is what you are confused about, to measure Vout you would connect one of the analog input/oscilloscope pins (either 1+ or 2+) of the Analog Discovery 2 to a spot on the breadboard where one of the legs of C3 is connected to RL.
For the analog measurement of Vin, this will be at the same location (i.e. column of 5 pins) where the leg of C2 is not connected to anything else in the circuit. This same column will also be where you provide the waveform generator input (either W1 or W2).
I would also recommend that you attach the ground connections as well as the 1- and 2- of the Analog Discovery 2 to the ground rails that you have on your breadboard for a cleaner measurement on the oscilloscope channels.
Thanks,
JColvin

Hi @tridot64,
I tried to find some sort of definitive answer, but I'm not readily finding a reason for why print is not working over printf or xil_printf in the software environment (I'm presuming that the print function uses 115200 baud by default which would match the default Zynq configuration, though I haven't ). Because the UART on Zynq devices use the ARM processor, this won't be a hardware issue specific to the Zybo Z7 but an issue with how Xilinx's libraries/compilers play with the ARM processors on their own SoCs.
Thanks,
JColvin

Hi @pulkit,
The application is trying to fit inside the block ram (BRAM) that is integrated with the FPGA, you will, as you already surmised, want to adjust the linker script.
You can do this by opening the lscript.ld that is directly below the main.cc you have open in your screenshot. Scroll down to the "Section to Memory Region Mapping" and adjust the Memory Region for each of the section names to "mig_7series_0_memaddr".
Let me know if you have any questions.
Thanks,
JColvin

The solution is to call XSpi_IntrGlobalDisable(&XSpiInstance) after XSpi_Start(&XSpiInstance).

Hi @toddk2,
I took a picture of the power brick that came with the Analog Discovery Pro ADP3450 and attached it to this post. Based on what it says, 230V at 60 Hz should be fine.
Let me know if you have any questions.
Thanks,
JColvin

Hi @HomaGOD,
The Basys 3 might be able to communicate with the Pmod BT2 via the Pmod BT2 IP core, though I don't know if the Basys 3 has enough memory for the application; we have a guide on how to use Pmod IP cores for Vivado and SDK (2019.1 and earlier) here, and a newer one that walks through setting up a design in Vivado and Vitis (2019.2 and later) here.
The Pmod WiFi will not work on the Basys 3 though because it does not have enough memory (and no external memory) to be able to hold the needed software to run the WiFi application.
Let me know if you have any questions.
Thanks,
JColvin

Hi @mirabelle275,
I haven't used Matlab or Simulink in combination with Xilinx's tools, so I'm not certain what you would need to do on that end of things.
As for the create_clock constraint, it does not actually create a clock. It just tells the Vivado software that this particular net should be treated as a clock while it goes through its various synthesis and optimization steps. Pin E3 itself on the Nexys A7 is connected to a 100 MHz oscillator on the board, so you cannot actually change this frequency. You would need to use a clock management tile to be able to create a different clock frequency from the 100 MHz line, though I don't know this would be done in MATLAB; this might be a good resource for you, https://www.mathworks.com/help/hdlcoder/ug/using-multiple-clocks-in-hdl-coder.html, though otherwise you'll probably need to ask on MATLAB Answers, https://www.mathworks.com/matlabcentral/answers/index/?s_tid=gn_mlc_an, to get more specific help.
Thanks,
JColvin

OK, Problem solved, thanks to a colleague at Grenoble-Alpes university. This issue is related to separators in files, which can cause problem with regional settings of Linux. Changing my settings from fr_FR to en_US solves the problem.
It is still strange that the Zybo board files work fine in fr_FR, and not the ZyboZ7.

Hi @canisio,
Pmod JF on the Zybo Z7-20 is an MIO Pmod, meaning that it is connected to the processing system/ARM core (PS) on the Zybo Z7 rather than the programmable logic (PL). You can choose in the Zynq IP in the MIO tab which peripherial type you want connected to the MIO pins associated with JF (only certain ones are connected, so for example for the Zybo Z7-20 only SPI1 has some MIO pin connections that work on JF whereas SPI0 does not).
You would then use the associated peripheral library like XGpioPs or XSpiPs to control these pins. You won't be able to add the Pmod itself to the block design, nor will you usually be able to directly use the Pmod libraries since they use AXI IP drivers, so some changes would need to be made to the Pmod library (since you can import it in SDK) in order for it to work with the MIO Pmod.
Let me know if you have any questions.
Thanks,
JColvin

Hi @canisio,
That is correct. MIO50 and MIO51 are connected to a couple of buttons on the Zybo Z7 (as I imagine you know), but then yes, you can use the XGpioPS drivers to control them. The preset for the Zynq IP block already sets MIO50 and 51 to GPIO, so you don't need to change anything in the block design itself. If you need it, Xilinx has an example on using XGpioPs here: https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/gpiops/examples/xgpiops_polled_example.c.
Let me know if you have any questions.
Thanks,
JColvin

Hi @Mathias
The instructions are long mostly because they are written to be fairly verbose and (ideally) clear.
Vitis should not be that big to install; or at least when I use the self-extracting web installer and only leave board options that I need checked, the final disk installation size of both Vivado and Vitis 2021.1 for me is just shy of 70 GB. Makes me yearn for the less than 15 GB size that 2015.4 was to be sure, but that's neither here nor there.
I asked another co-worker to make a DDR demo and they're hoping to get it completed in the next couple of weeks (in between all of their other tasks and making sure the documentation/tutorial aspect is clean).
Let me know if you have any questions.
Thanks,
JColvin

Hi @Mathias,
If you are only wanting simple example that has the DDR memory being tested, you can follow this guide which walks through setting up DDR memory and MIG on the Arty S7 board in Vivado and exporting it into Vitis: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi. When choosing an application project in Vitis, there is a premade Memory Test which then does a test write and read back of data to the DDR.
As for a more pragmatic design that doesn't rely on the processor (or one that does) Digilent does not currently have one that I know of, though I will ask for one.
Thanks,
JColvin

Hi @Willard,
The 12 MHz clock is coming from IC10 which is a 12.000 MHz oscillator that also provides the 12 MHz for the FT2322 chip. This particular IC is on the "intentionally left blank" page of the schematic, but you can see the actual IC10 on the underside of the Arty S7 between Pmod JA and Pmod JB. There isn't anything fancy about the connection; if you hold up the board at the right angle, you can see the trace running from IC10 through a couple of resistors and then into F14 on the FPGA itself.
The 100 MHz oscillator that is recommended to be used for the MIG to run DDR based designs is IC3 on the underside of the board between BTN0 and the 6-pin SPI header (J7). That one is visible on page 5 of the Arty S7 schematic, https://digilent.com/reference/_media/reference/programmable-logic/arty-s7/arty_s7_sch-rev_e.pdf.
Let me know if you have any questions.
Thanks,
JColvin

After doing some more research, I believe that the issue is related to the Raspberry Pi 4's processor not supporting clock stretching.
And using the recommended solution of a software-based I2C did not work for me, and I don't have the time to research this further... (I don't really need the AQS for my hobby project!)
I have more links I can dig up, but give me time...

Hi @Ardelle Froeliger,
If you want to load a bitstream to a board, you would first need to create a project for it in the appropriate Xilinx software (usually Vivado for Digilent's current board offerings), and then click on the appropriate in-software button to generate a bitstream. If you made a project with only HDL you could follow this guide to program the board with the bitstream, https://digilent.com/reference/programmable-logic/guides/getting-started-with-vivado, otherwise if you are using a block design flow this guide would be more helpful for you: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi.
Let me know if you have any questions about this.
Thanks,
JColvin

I've started a thread for people wanting to know how to use the DDR memory on their FPGA boards. I want this to be interactive as it's not possible to provide  a single demo project that works for all boards and all versions of Vivado. To get this started, I've provided a tutorial in the file XilinxDDR_Tutorial_Part_1.txt. As, the name implies this is just the beginning of the tutorial, but if you get through it, you will have a working DDR design running on your hardware.
Not everyone ( perhaps no one? ) will be happy with having to plow through a long text file but there are reasons for why I am presenting this material in this format. Perhaps, I will try and pretty the content up at a later time, if the topic is popular enough.
[Update] I've posted part 2 of the Tutorial. You can follow steps to creating a more useful DDR design by reading the file XilinxDDR_Tutorial_Part_2.txt. This isn't the end.
[Update] I've posted part 3 of the Tutorial in which we look at performance and simulation.
 
imp_top.v imp_top.xdc
XilinxDDR_Turorial_Part_1.txt
NexysVideoDdrDemo.vhd NexysVideoDdrDemo.xdc UART_DEBUGGER2.vhd XilinxDDR_Turorial_Part_2.txt YASUTX.vhd
 
NexysVideoDdrTest.vhd XilinxDDR_Turorial_Part_3.txt