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gibberish on Hello world project on Vitis 2020.2 and Zybo z7 10


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I am a newbie to FPGA and all things related. I installed all the board files from the repository. Created my block design and ran the block automation. I created a HW platform and a SW application with the template. I put my Zybo Z7 10 on JTAG mode. i can verify that the UART prints out data when it passes a print statement. But the printed value doesnt correspond to what is supposed to be in it. I have attached necessary screenshots. I am guessing that i have an error with the UART. To make sure my cable wasnt at fault, I reset the system to get the OOB image "initializing init:done ..".

Both the Tera term and the vitis terminal gave the same output.

VIvado version 2020.2

OS: Windows 11 


Thanks in Advance.






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Hi @tridot64,

I tried to find some sort of definitive answer, but I'm not readily finding a reason for why print is not working over printf or xil_printf in the software environment (I'm presuming that the print function uses 115200 baud by default which would match the default Zynq configuration, though I haven't ). Because the UART on Zynq devices use the ARM processor, this won't be a hardware issue specific to the Zybo Z7 but an issue with how Xilinx's libraries/compilers play with the ARM processors on their own SoCs.


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