jpeyron
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Posts posted by jpeyron
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Hi @Ben007,
Welcome to the forums. We do not have a step by step tutorial on using the XADC. Here is the XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide as a reference. We do have an HDL XADC demo here for the Nexys 4 DDR. Here is a forum thread that uses microblaze with the XADC which also includes sdk code. This should be useful to get you started if you are wanting to use microblaze. What DAC are you using? Something like the Pmod DA4? We do not have an IP core for the Pmod DA4 but we do have an ip core for the Pmod DA1. Here is the resource center for the Nexys 4 DDR.
thank you,
Jon
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Hi @rwheadon,
I have not had much experienced with the ethernet with fpga's beyond using the echo server. I used wireshark on the echo server project and I attached the file below. I did not get the checksum incorrect with the UDP. Were you able to get the echo server to echo at the 1Gbps? I tried the peripherals test and had it hang on the axiethernetsgdmaInterexample for the axi-ethernet as well as the interrupt for the axi-timer multiple times. I did get it once to pass the ethernet test without changing anything from the other test runs. I have used the peripherals test on different project and had the axi-interrupt and other peripherals hang before while being able to work with the hardware/software without issue. I would suggest to reach out to xilinx and see if this is an sdk issue.
thank you,
Jon
wireshark_nexys_video_echo_server.pcapng
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Hi @zazou,
To clarify your most recent post. You would like help incorporating the attached vhdl code to work with the zynq processor. Is that correct?
thank you,
Jon
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Hi @rwheadon,
Have you tried the changing the phy speed to 100? You can do this by following step 10.2 in the tutorial by rick clicking the bsp and selecting the lwip and then selecting temac_adapter_options → phy_link_speed. Here you will need to change CONFIG_LINKSPEED_AUTODETECT to CONFIG_LINKSPEED100. Could also you try this vhdl ethernet project here? I also made an ethernet project in Vivado 2015.4 for the Nexys Video here. I will test to make sure the project works tomorrow.
thank you,
Jon
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Hi @hardlyhacker,
Here is the Nexys Video - Getting Started with Microblaze Servers tutorial that walks you through setting up an echo server and will verify if the ethernet is working.
thank you,
Jon
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Hi @zazou,
The zynq processor can make dev work easier especially for those that are more comfortable with microprocessors and c/c++ coding. It also helps make more complex components easier to work with like ethernet and ddr3 that are directly connected to the arm processors. The Arty-Z7-20 has an zynq hdmi in project already completed on the resource center here .
cheers,
Jon
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Hi @zazou,
Here is a forum thread that discusses using the add a module and the gpio ip core process. Could you be more specific about the project are you trying to making a pure vhdl project using the switches or buttons to control the TLC5940 or are you trying to use the zynq processor with the add a module and gpio ip core to control the TLC5940 in sdk?
thank you,
Jon
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Hi @zazou,
Electrically the TLC5940 should work without an issue with the Arty-z7-20. You will need to make your own serial controller in hdl(verilog/vhdl) to interact with the TLC5940. You can make a full hdl(verilog/vhdl) design or have the serial controller connect to the zynq processor through the axi using the add module function in vivado. I am not sure if the zynq processor design will reach the desired 30 MHZ serial communication. A full HDL design will reach the desired 30 MHZ serial communication.
thank you,
Jon
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Hi @mohammadhgh,
When you run block automation on the zynq processor it has the apply board pre-set box checked. My understanding is that the board files become the default setting.
thank you,
Jon
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Hi @dbkincaid,
That is an interesting suggestion. I have passed this on to the appropriate co-workers.
cheers,
Jon
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I am tagging the engineer that handles this. They are out of the office today so I would not expect a response until tomorrow or at the latest early next week ( @Bianca).
cheers,
Jon
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HI @kpax,
I am sorry to hear you are still having issues with connecting the Arty Artix 7 development board. Since Adept 2 is not able to see the Arty this leads me to believe that this is an EEPROM issue. I am tagging the engineer that handles this issue( @Bianca). The Xilinx Platform cable USB should work with Vivado as long as the EEPROM is correctly working.
cheers,
Jon
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Hi @kpax,
Are you able to program other boards or see data from a compatible smart phone with the USB A to Micro-B cable you are using? Concerning the FTDI drivers, the FTDI drivers should have downloaded and installed the first time you connected the Arty to your computer. The FTDI drivers can be downloaded from here. Have you used another computer with Vivado? Please download Adept 2 here and see if this software can connect to your Arty(make sure Vivado is not connected to your Arty in any way). I have included some screen shots below. Also to clarify when you connect the Arty the power led ld11 turns on?
cheers,
Jon
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Hi @smarano,
I am not aware of another program other that Vivado that can program the flash. Unfortunately, Adept 2 will not program the flash. I do know that you can program the flash from the stand alone hardware manager in Vivado.
thank you,
Jon
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Hi @brhack,
Welcome to the forums! Could you elaborate more on your thread. Not 100% sure what V5 or V7 is. Are you talking about Virtex 5 and Virtex 7? Or are you referring to Vivado 2015 and Vivado 2017? It depends on what you are looking to develop as well as what platform to what board you should get. If you are looking into Zynq there is the Arty-Z7, Zybo, Zedboard or the Pynq board. If you are looking for Artix 7 only then I would look at the Arty, Basys 3, Cmod A7, Nexys 4DDR or the Nexys Video.I believe all of these boards have a quad spi flash. I am not sure which if any of the fpga boards work with labview. I have reached out to a couple of my co-workers that will know more about the compatibility with labview( @AustinStanton, @JColvin).
cheers,
Jon
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Communication à travers le shield de la carte Arty
in Add-on Boards
Posted
Hi @zazou,
can you also include your xdc you are using? I also changed a couple of things in your VHDL code. Here is a project done in Vivado 2017.4 that uses the add a module to the zynq design. I created one port to show how to do it but left the rest to you to set up. Here is an xilinx forum thread that talks about using the add a module process.
thank you,
Jon