asmi

There is no BootROM in Artix. Looking at names, it looks like you're trying to synthesize one of SiFive cores, so I would recommend you ask them for support, as I assume abovementioned bootROM is going to contain some kind of startup code for their CPU core. I don't think Digilent support folks will be able to help you much on that matter, but if you want, you can of course wait until they respond.

DXF and gerbers are two different things.

Well add them yourself then. What's the big deal?

Nowhere - they are not publicly available.

I meant program_ftdi.

Not anymore. That's because program_ftdi was released only about a year ago, before that you had no option but to license this from Digilent.

Can you please let us know why would you want to do that? Just curious.

At the minimum, I would require AI-generated posts to be marked as such. It's hard enough to figure out what human user is actually trying to achieve (as opposed to what he says he wants to achieve, or often what he thinks he's trying to achieve), but wasting mental energy on unraveling AI posts is a bit too much to ask in my opinion considering many (including me) are trying to help people here voluntarily. With that, I don't really see how AI posts will help since anyone willing to get such responses can "ask" such AI system directly. That said, I would simply forbid such posts altogether as in my opinion forums are meant for human beings.

It sits on WFE after reset anyways, not sure if it consumes any power.

It's impossible as far as I know. You will have to connect another QSPI device to PL pins.

How else would you test a QSPI controller HDL if not by connecting it to actual QSPI device? That is irrelevant as the goal is to test his own QSPI controller, and not expose PS controller outside. And a side question - what does SD controller have to do with QSPI?

Maybe you should read it again, because it seems that you've got this whole EMIO thing the wrong way around - it's purpose is to route PS peripherals to PL pins (because there are much more PS peripherals than there are MIO pins in a package), and not MIO pins to PL peripherals. As far as I know, there is no way to route MIO pins to PL at all. Therefore if flash device is connected to MIO pins (which all Zynq boards I know of do), you can't access it from PL (aside from going through AXI bus and a PS QSPI controller of course).

Odds are the flash is connected to MIO pins (otherwise Zynq won't be able to boot from it), in this case this flash memory is not available to PL at all.

Not to ground, but to Vccio (+3.3 V)!

Yes it can, but with some caveats. See my post above for one such way, another way is to use TMDS OUT (which is available at Vccio of 3.3V) and then convert it into regular LVDS using a level converter IC (for example, TI's TMDS1204 or TDP1204).

Documentation says that you can receive an LVDS signal on any differential pair regardless of Vccio (that's due to the way LVDS receiver is implemented in silicon). However that's not the full story, there are a bunch of conditions - quoting from UG471: The most important of those is (a), as it requires you to have an external termination resistor, which ideally needs to be placed as close as possible to receiver. Not sure what kind of speed can one realistically reach in that kind of environment, but I suspect that you aren't likely to get anywhere near full 1.25 Gbps per pair. BUT! JXADC PMOD connector is connected to bank 15, which is powered by VADJ adjustable power supply, so you can technically implement any IO standard that is available in IO cells if you set up your VADJ accordingly. However none of IO pairs connected to JXADC is actually clock-capable, so you can't use JXADC to receive source-syncronous signals, but you can still output them. My guess is that JXADC was designed primarity for LVDS output (as well as analog connections of course).

Interesting, moreso that this board went through so many revisions (I have the original Arty, back from the days when it was called simply "Arty", not "Arty A7"), and yet this wasn't changed. But I guess don't fix what ain't broken 😉

I see no reason to suspect malice when simple incompetence would do. Do you really expect everyone in sales and marketing department to be experts on FPGAs?

I chuckle every time I see/hear them mention that. In what other industry one can call $800 chips "cost optimized" with the straight face and won't end up promptly laughed away?

A lot of people are prototyping DSP algorithms in Python or Matlab because they have facilities for rapid prototyping, as well as great visualization tools which allow to quickly figure out if algorithm does what it's meant to do. The key here is not the language, but the algorithm itself. That's what I think he meant.

Thank you, especially for being proactive. I don't search for these on purpose, but I'm often asked about your products, so I have to refer to your store descriptions since I can't remember each and every detail about all of them. Yeah, I've been pondering the relevance of this information to pre-designed boards as well, and it didn't make much sense to me, but I frankly forgot to mention that after I was asked for umteenth time about getting access to GTPs on Arty A7 boards, so that I went onto its' store page searching for cues as to where these questions might be coming from.

Some Artix devices have higher DSP/logic and BRAM/logic ratio, which might be important for some designs, but otherwise (ignoring GTPs) they complement each other as far as packages/densities go, but of course that fact is not relevant for those who only buy premade boards. Basically Spartan-7 tend to have more IOs available for the same density, while Artix focuses more on computing resources. For example, S75/S100 devices in 484 and 676 ball packages have enough IO to create a moster dual-channel SODIMM DDR3 controller for massive 128 bit of a total data bus running at 400 MHz, while on Artix side this is only possible with the largest A200T device. Artix devices also exist in speed grade 3, which are a bit faster than SG2 and have some unique capabilities (like driving DDR3 at 533 MHz instead of "usual" 400 MHz which is what most Artix-7 and all Spartan-7 devices are capable of).

I know that, my question was why their presence is advertised as a feature, while they infact are not available? That statement is not even close to being true. Some people choose boards specifically for MGTs exactly because they need them, so it can be a nasty surprise if they read the "features" section and conclude that they are available (otherwise what's the point to advertise them?), and will end up getting a bad surprise to find out that they are infact not available.

Here is a section of Arty A7 photo: What are these things for? The ones on the bottom look like differential pairs, but since all other vias are covered with solder mask, these were obviously left open for a reason. Now I'm curious what these are for :) Another unrelated question - the "Features" page of Arty A7 board advertizes presence of GTP transcievers: The problem is that it's factually incorrect, because the CSG324 package doesn't bond out any MGTs as per Xilinx/AMD datasheet:

I forgot to mention that Digilent also has Pmod I2S2: https://digilent.com/shop/pmod-i2s2-stereo-audio-input-and-output/ that houses an audio ADC and DAC ICs, which could be used to add audio capabilities to boards. I've never used it myself, but Digilent provides examples for Arty A7, S7 and Cora Z7 boards, so that might be something worth looking at for you. The cheapest from those is Arty S7, having worked with Spartan-7 devices myself (here is one board I designed with that device: https://www.eevblog.com/forum/fpga/custom-spartan-7-board-for-beginners/ ), I would highly recommend S7-50 variant for a beefier FPGA because S7-25 device is rather small - for example just DDR3 controller will eat up to 1/3 of all resources available in this device, so it won't leave much space for your own custom code, which it would only take about 15% of FPGA resources, leaving quite a bit for your stuff.