kr.mk1

Hello there , I am trying to validate my own written Qspi RTL design. how can i access the Zynq Qspi flash to read write by my own design Thanks

Hi @JColvin thanks I am Using the https://www.xilinx.com/products/boards-and-kits/zcu104.html FPGA Board ,i just want to validate the design with some real hardware

Thanks @D@n , I am using ZYNQ UltraScale+ , Can u tell me how can i access the Qspi Falsh via EMIO or MIO with all 4 io line, sclk and cs. when i am enabling the qspi flash and spi IO i am only able to pin out the standard spi interface pin like , sclk, miso, mosi and cs. thanks and regards

I write RTL (Verilog )code for Quad SPI Protocol, on simulation its working . Can Anyone please suggest me the suitable hardware for the validation.