attila

Hi @jabitti For hFE select Measure: Ic/Ib

Hi @yusuke_Adv Yes, dwf.FDwfAnalogIOChannelNodeSet(hdwf, 0, 0, c_double(1.2))

Hi @JosefS It can decode the following 1-wire data. This cannot be changed by the user. Reset Presence Read ROM [0x33] Skip ROM [0xCC] Match ROM [0x55] Search ROM [0xF0] Overdrive Skip ROM [0x3C] Overdrive Match ROM [0x69] Alarm Search [0xEC] Convert T [0x44] Resume [0xA5] Write Scratchpad [0x4E] Read Scratchpad [0xBE] Recall [0xB8] Read Power Supply [0xB4] Command [0x..] Family: 0x.. SN LSB: 0x.. SN MSB: 0x.. CRC: 0x.. Data: 0x..

Hi @danaur See the Help tab and examples.

Hi @Ondrej Scope.Time.taken

Hi @yusuke_Adv See the WF app Help and SDK manual pdf

Hi @yusuke_Adv If you are referring to the Sync mode in Logic Analyzer see the WF SDK/ samples/ py/ DigitalIn_Sync.py Another option would be using the external clocking mode which is available in mixed mode. For this configure the configure the analog-in to use trigger line as clock and for digital-in use FDwfDigitalInClockSourceSet(, DwfDigitalInClockSourceExternal2) so digital-in to use analog-in sampling.

Hi @Mathias G. What is the frequency of the external clock you use? Using your script I've connected the following and it seems to be working. DIO 11 to Trig1 DIO 9 to Trig2 DIO 5 to C1

Hi @Walter76 It looks like it is a filter on C2. Could you attach a photo with your setup? You could also test it with Wavegen and Scope using a square signal. The open and short compensation is available in the Impedance Analyzer. The NA capture should look like this, with -3dB around 12MHz. See the following about the device bandwidth : https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide#scope_spectral_characteristics https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide#awg_spectral_characteristics

Hi @corestar Other devices should work even Win7 as it is no longer supported so it is not recommended to use it. Thank you for the observation, we should add later (or 11) and ARM64 (except ADP5250).

Probably to reduce the internal and input capacitance.

Hi @Walid Yes, this is normal. In Analog Discovery 3, the oscilloscope input ranges are switched by relays. The electrical endurance is rated at 10^5, but since it is used to switch very low current and capacitance, we can take the mechanical durability of 10^8 (100M) as a guide.

Hi @Robert White Instead of software delay you could also use hardware delay with FDwfAnalogOutWaitSet

Hi @Walid Yes, newer devices use 16bit samples, see:

Hi @WojtekO For instance the Shcore is available in Win 8.1 and newer.

Hi @Musicsteve The dropdown options should show up on click. What OS browser are you using? The download links are also available here: https://digilent.com/reference/software/waveforms/waveforms-3/change-logs/3-20-1 or the latest beta version here:

Hi @JimR2 +DPS3340 is fixed in the latest version: Two Digital Discoveries are NOT supported, yet, since the WaveForms Logic Analyzer is limited to 32-bit samples. However, it was and it is possible to create custom app/script which controls multiple devices. Dual mode is recommended for devices with clock IO capability, ADP3X50, AD3 or newer. Without a reference clock, signals will have jitter and drift over time.

Hi @leonvs You could eventually use the DIO/DIN pull up-down to shift the input signals a bit, by about 0.4%/10%

Hi @WojtekO The ADP5000 support dll (C:\Windows\System32\dadp5capi.dll) is dynamically loaded by dwf.dll, which is used by WF. Probably the dadp5capi.dll load fails due to some dependency. Edit: This is installed by:

Hi @cdupuis I fixed this today after your post.

Hi @leonvs Threshold voltage cannot be set independently of VIO. The threshold value is set by the supply voltage (VIO) of the FPGA bank. The threshold and hysteresis difference is likely due to the device's FPGA IOs. Digital Discovery uses Spartan6 and ADP3450 Zynq (Artix7). DIO frontends are similar, see: https://digilent.com/reference/test-and-measurement/digital-discovery/reference-manual#io_level_translators

Hi @Mathias G. See the following: Or you can use the reference clock option:

Hi @JerryM Could you use newer OS ? The network support probably requires newer software version and this requires newer glibc than CentOS7 has.

Hi @Robert White I don't see in this code the Scope being fully configured and started. You may want to set the sampling rate, trigger position, number of samples... Then call FDwfAnalogInConfigure to start it before FDwfAnalogOutConfigure, with a delay if you are capturing pre-trigger samples to perform buffer refill, since it will look for trigger event only after prefill is done. The default 'acqmodeSingle' will restart the capture.

Hi @leonvs So far, the DIO input logic threshold on all our T&M devices is given by the VIO voltage. Shielded or ground-twisted signal lines should be used to reduce crosstalk, such as: https://digilent.com/reference/test-and-measurement/digital-discovery/reference-manual?redirect=1#accessories