Hi @artvvb
Thanks for your reply.
Indeed, you've got the core concept correct. The HLS IP continuously reads data from the ZmodScopeController until a signal on one of the two channels surpasses a predefined threshold. Once this condition is met, it triggers the episode_processing function to execute N_STEPS times. In each iteration, the HLS IP sends a distinct pulse to the ZmodAWGController and forwards the next 2000 samples from the input to the Processing System (PS) via DMA. The use of the internal stream was just a desperate attempt (😁) to make it work, same for the external FIFO. Do they make sense?
The repetition of episode_processing N_STEPS times is only related to this simplified version I'm using for debugging. In reality, the IP conducts specific data processing on the inputs received from the ADC. It then determines the appropriate outputs to send to the DAC based on this analysis. Each of these operations must occur sequentially, directly after the preceding one, upon exceeding the threshold, hence the multiple iterations.
Not sure I got everything here, I've implemented this function to try to check the DMA register, is this what you meant?
/ -----------------------------------------------
// DMA Base Address
#define DMA_BASE_ADDR XPAR_AXI_DMA_0_BASEADDR
// DMA Register Offsets
#define S2MM_DMACR_OFFSET 0x30 // Control Register
#define S2MM_DMASR_OFFSET 0x34 // Status Register
// DMA Status Register Bit Masks
#define HALTED_MASK 0b00000000000000000000000000000001
#define IDLE_MASK 0b00000000000000000000000000000010
#define DMA_INT_ERROR_MASK 0b00000000000000000000000000010000
#define DMA_SLV_ERROR_MASK 0b00000000000000000000000000100000
#define DMA_DEC_ERROR_MASK 0b00000000000000000000000001000000
#define SG_INT_ERROR_MASK 0b00000000000000000000000100000000
#define SG_SLV_ERROR_MASK 0b00000000000000000000001000000000
#define SG_DEC_ERROR_MASK 0b00000000000000000000010000000000
#define IOC_IRQ_MASK 0b00000000000000000001000000000000
#define DLY_IRQ_MASK 0b00000000000000000010000000000000
#define ERR_IRQ_MASK 0b00000000000000000100000000000000
// Define macros for accessing registers
#define DMA_S2MM_DMACR (*((volatile unsigned int*)(DMA_BASE_ADDR + S2MM_DMACR_OFFSET)))
#define DMA_S2MM_DMASR (*((volatile unsigned int*)(DMA_BASE_ADDR + S2MM_DMASR_OFFSET)))
void check_dma_status() {
volatile unsigned int status = DMA_S2MM_DMASR;
xil_printf("Checking DMA Status...\r\n");
xil_printf("DMA Status Register: 0x%X\r\n", status);
// Check if the DMA is halted
if (status & HALTED_MASK) {
xil_printf("DMA is halted.\r\n");
} else {
xil_printf("DMA is running.\r\n");
}
// Check if the DMA is idle
if (status & IDLE_MASK) {
xil_printf("DMA is idle.\r\n");
} else {
xil_printf("DMA is active.\r\n");
}
// Check for different types of errors
if (status & DMA_INT_ERROR_MASK) {
xil_printf("DMA Internal Error detected.\r\n");
}
if (status & DMA_SLV_ERROR_MASK) {
xil_printf("DMA Slave Error detected.\r\n");
}
if (status & DMA_DEC_ERROR_MASK) {
xil_printf("DMA Decode Error detected.\r\n");
}
if (status & SG_INT_ERROR_MASK) {
xil_printf("SG Internal Error detected.\r\n");
}
if (status & SG_SLV_ERROR_MASK) {
xil_printf("SG Slave Error detected.\r\n");
}
if (status & SG_DEC_ERROR_MASK) {
xil_printf("SG Decode Error detected.\r\n");
}
// Check for interrupts
if (status & IOC_IRQ_MASK) {
xil_printf("Interrupt on Complete detected.\r\n");
}
if (status & DLY_IRQ_MASK) {
xil_printf("Interrupt on Delay detected.\r\n");
}
if (status & ERR_IRQ_MASK) {
xil_printf("Error Interrupt detected.\r\n");
}
}
And also, I introduced a GPIO IP to check the control signals of the ADC and DAC. This it the full code:
#include <stdio.h>
#include "xil_printf.h"
#include "xaxidma.h"
#include "xparameters.h"
#include "xlevel_1_hls_stream_simplified.h"
#include "xgpio.h"
// Define GPIO Device instance
XGpio Gpio;
u32 Data;
#define GPIO_DEVICE_ID XPAR_GPIO_0_DEVICE_ID
XAxiDma AxiDma;
const int AXI_DMA_ID = XPAR_AXI_DMA_0_DEVICE_ID;
const int DEV_ID = XPAR_LEVEL_1_HLS_STREAM_S_0_DEVICE_ID;
#define N_STEPS 1
#define MAX_VAL 32767 // Which corresponds to 5V
#define TH 500
#define N_INPUT 8
#define N_RUNS 20
#define RX_BUFFER XPAR_PS7_DDR_0_S_AXI_BASEADDR
typedef u32 out_data_t;
u32 recv_buffer[ N_STEPS*N_INPUT/2 ] __attribute__((aligned(4)));
// -----------------------------------------------
// DMA Base Address
#define DMA_BASE_ADDR XPAR_AXI_DMA_0_BASEADDR
// DMA Register Offsets
#define S2MM_DMACR_OFFSET 0x30 // Control Register
#define S2MM_DMASR_OFFSET 0x34 // Status Register
// DMA Status Register Bit Masks
#define HALTED_MASK 0b00000000000000000000000000000001
#define IDLE_MASK 0b00000000000000000000000000000010
#define DMA_INT_ERROR_MASK 0b00000000000000000000000000010000
#define DMA_SLV_ERROR_MASK 0b00000000000000000000000000100000
#define DMA_DEC_ERROR_MASK 0b00000000000000000000000001000000
#define SG_INT_ERROR_MASK 0b00000000000000000000000100000000
#define SG_SLV_ERROR_MASK 0b00000000000000000000001000000000
#define SG_DEC_ERROR_MASK 0b00000000000000000000010000000000
#define IOC_IRQ_MASK 0b00000000000000000001000000000000
#define DLY_IRQ_MASK 0b00000000000000000010000000000000
#define ERR_IRQ_MASK 0b00000000000000000100000000000000
// Define macros for accessing registers
#define DMA_S2MM_DMACR (*((volatile unsigned int*)(DMA_BASE_ADDR + S2MM_DMACR_OFFSET)))
#define DMA_S2MM_DMASR (*((volatile unsigned int*)(DMA_BASE_ADDR + S2MM_DMASR_OFFSET)))
void check_dma_status() {
volatile unsigned int status = DMA_S2MM_DMASR;
xil_printf("Checking DMA Status...\r\n");
xil_printf("DMA Status Register: 0x%X\r\n", status);
// Check if the DMA is halted
if (status & HALTED_MASK) {
xil_printf("DMA is halted.\r\n");
} else {
xil_printf("DMA is running.\r\n");
}
// Check if the DMA is idle
if (status & IDLE_MASK) {
xil_printf("DMA is idle.\r\n");
} else {
xil_printf("DMA is active.\r\n");
}
// Check for different types of errors
if (status & DMA_INT_ERROR_MASK) {
xil_printf("DMA Internal Error detected.\r\n");
}
if (status & DMA_SLV_ERROR_MASK) {
xil_printf("DMA Slave Error detected.\r\n");
}
if (status & DMA_DEC_ERROR_MASK) {
xil_printf("DMA Decode Error detected.\r\n");
}
if (status & SG_INT_ERROR_MASK) {
xil_printf("SG Internal Error detected.\r\n");
}
if (status & SG_SLV_ERROR_MASK) {
xil_printf("SG Slave Error detected.\r\n");
}
if (status & SG_DEC_ERROR_MASK) {
xil_printf("SG Decode Error detected.\r\n");
}
// Check for interrupts
if (status & IOC_IRQ_MASK) {
xil_printf("Interrupt on Complete detected.\r\n");
}
if (status & DLY_IRQ_MASK) {
xil_printf("Interrupt on Delay detected.\r\n");
}
if (status & ERR_IRQ_MASK) {
xil_printf("Error Interrupt detected.\r\n");
}
}
int InitializeDMA() {
XAxiDma_Config *CfgPtr;
int Status;
CfgPtr = XAxiDma_LookupConfig(AXI_DMA_ID);
if (!CfgPtr) {
xil_printf("No config found for DMA %d\r\n", AXI_DMA_ID);
return XST_FAILURE;
}
Status = XAxiDma_CfgInitialize(&AxiDma, CfgPtr);
if (Status != XST_SUCCESS) {
xil_printf("DMA Initialization failed %d\r\n", Status);
return XST_FAILURE;
}
if (XAxiDma_HasSg(&AxiDma)) {
xil_printf("Device configured as SG mode \r\n");
return XST_FAILURE;
}
XAxiDma_Reset(&AxiDma);
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA);
XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DMA_TO_DEVICE);
return XST_SUCCESS;
}
int main() {
XLevel_1_hls_stream_simplified Instance;
XLevel_1_hls_stream_simplified_Config *ConfigPtr;
int status;
u32 th;
u32 *DataBufferPtr = (u32 *)recv_buffer;
xil_printf("Let's start!\n\r");
// Initialize GPIO device
int Status = XGpio_Initialize(&Gpio, GPIO_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
// Set all pins as input (for 7 signals use 0b1111111 which is 0x7F in hexadecimal)
XGpio_SetDataDirection(&Gpio, 1, 0x7F);
// Read the state of the input pins
Data = XGpio_DiscreteRead(&Gpio, 1);
// Print the states of each signal
xil_printf("Control signals Before initializing the HLS ip.\n\r");
printf("Control Signals State:\n");
printf("sInitDoneDAC: %lu\n", (Data >> 0) & 0x1);
printf("sConfigError: %lu\n", (Data >> 1) & 0x1);
printf("sRstBusy: %lu\n", (Data >> 2) & 0x1);
printf("sInitDoneADC: %lu\n", (Data >> 3) & 0x1);
printf("sConfigError: %lu\n", (Data >> 4) & 0x1);
printf("sInitDoneRelay: %lu\n", (Data >> 5) & 0x1);
printf("sDataOverflow: %lu\n", (Data >> 6) & 0x1);
check_dma_status();
xil_printf("-----------------------------------.\n\r");
ConfigPtr = XLevel_1_hls_stream_simplified_LookupConfig(DEV_ID);
status = XLevel_1_hls_stream_simplified_CfgInitialize(&Instance, ConfigPtr);
if (status == XST_SUCCESS) {
xil_printf("Successfully configured HLS core.\n\r");
}
status = InitializeDMA();
if (status != XST_SUCCESS) {
xil_printf("Data DMA In Initialization Failed\r\n");
return XST_FAILURE;
}
XLevel_1_hls_stream_simplified_InterruptGlobalDisable(&Instance);
XLevel_1_hls_stream_simplified_Set_th(&Instance, TH);
th = XLevel_1_hls_stream_simplified_Get_th(&Instance);
xil_printf("TH set to: %lu\n\r", th);
// Read the state of the input pins
Data = XGpio_DiscreteRead(&Gpio, 1);
// Print the states of each signal
xil_printf("Control signals Before Starting the HLS ip.\n\r");
printf("Control Signals State:\n");
printf("sInitDoneDAC: %lu\n", (Data >> 0) & 0x1);
printf("sConfigError: %lu\n", (Data >> 1) & 0x1);
printf("sRstBusy: %lu\n", (Data >> 2) & 0x1);
printf("sInitDoneADC: %lu\n", (Data >> 3) & 0x1);
printf("sConfigError: %lu\n", (Data >> 4) & 0x1);
printf("sInitDoneRelay: %lu\n", (Data >> 5) & 0x1);
printf("sDataOverflow: %lu\n", (Data >> 6) & 0x1);
check_dma_status();
xil_printf("-----------------------------------.\n\r");
u32 bytes_to_read = N_STEPS * N_INPUT * sizeof(u32) / 2;
xil_printf("Bytes to read: %d\n\r", bytes_to_read);
XLevel_1_hls_stream_simplified_Start(&Instance);
xil_printf("Ready to go\n\r");
// Read the state of the input pins
Data = XGpio_DiscreteRead(&Gpio, 1);
// Print the states of each signal
xil_printf("Control signals After Starting the HLS ip.\n\r");
printf("Control Signals State:\n");
printf("sInitDoneDAC: %lu\n", (Data >> 0) & 0x1);
printf("sConfigError: %lu\n", (Data >> 1) & 0x1);
printf("sRstBusy: %lu\n", (Data >> 2) & 0x1);
printf("sInitDoneADC: %lu\n", (Data >> 3) & 0x1);
printf("sConfigError: %lu\n", (Data >> 4) & 0x1);
printf("sInitDoneRelay: %lu\n", (Data >> 5) & 0x1);
printf("sDataOverflow: %lu\n", (Data >> 6) & 0x1);
check_dma_status();
xil_printf("-----------------------------------.\n\r");
Xil_DCacheFlushRange((UINTPTR)DataBufferPtr, bytes_to_read);
status = XAxiDma_SimpleTransfer(&AxiDma, (UINTPTR)DataBufferPtr, bytes_to_read, XAXIDMA_DEVICE_TO_DMA);
if (status != XST_SUCCESS) {
xil_printf("Failed to start DMA transfer\r\n");
xil_printf("Status %d", status);
return XST_FAILURE;
}
while (!XLevel_1_hls_stream_simplified_IsDone(&Instance));
xil_printf("HLS is done. \n\r");
// Read the state of the input pins
Data = XGpio_DiscreteRead(&Gpio, 1);
// Print the states of each signal
xil_printf("Control signals After the HLS ip is done.\n\r");
printf("Control Signals State:\n");
printf("sInitDoneDAC: %lu\n", (Data >> 0) & 0x1);
printf("sConfigError: %lu\n", (Data >> 1) & 0x1);
printf("sRstBusy: %lu\n", (Data >> 2) & 0x1);
printf("sInitDoneADC: %lu\n", (Data >> 3) & 0x1);
printf("sConfigError: %lu\n", (Data >> 4) & 0x1);
printf("sInitDoneRelay: %lu\n", (Data >> 5) & 0x1);
printf("sDataOverflow: %lu\n", (Data >> 6) & 0x1);
check_dma_status();
xil_printf("-----------------------------------.\n\r");
while (XAxiDma_Busy(&AxiDma, XAXIDMA_DEVICE_TO_DMA));
xil_printf("DMA is done. \n\r");
Xil_DCacheInvalidateRange((UINTPTR)DataBufferPtr, bytes_to_read);
xil_printf("Received data: ");
for (int i = 0; i < N_STEPS * N_INPUT / 2; i++) {
if (i > 0) xil_printf(", ");
if (i % 1000 == 0) xil_printf("%d", DataBufferPtr[i]);
}
xil_printf("\n\r");
return 0;
}
And this is what I see as output:
Let's start!
Control signals Before initializing the HLS ip.
Control Signals State:
sInitDoneDAC: 1
sConfigError: 0
sRstBusy: 0
sInitDoneADC: 1
sConfigError: 0
sInitDoneRelay: 1
sDataOverflow: 1
Checking DMA Status...
DMA Status Register: 0x1
DMA is halted.
DMA is active.
-----------------------------------.
Successfully configured HLS core.
TH set to: 500
Control signals Before Starting the HLS ip.
Control Signals State:
sInitDoneDAC: 1
sConfigError: 0
sRstBusy: 0
sInitDoneADC: 1
sConfigError: 0
sInitDoneRelay: 1
sDataOverflow: 1
Checking DMA Status...
DMA Status Register: 0x1
DMA is halted.
DMA is active.
-----------------------------------.
Bytes to read: 16
Ready to go
Control signals After Starting the HLS ip.
Control Signals State:
sInitDoneDAC: 1
sConfigError: 0
sRstBusy: 0
sInitDoneADC: 1
sConfigError: 0
sInitDoneRelay: 1
sDataOverflow: 1
Checking DMA Status...
DMA Status Register: 0x1
DMA is halted.
DMA is active.
-----------------------------------.
HLS is done.
Control signals After the HLS ip is done.
Control Signals State:
sInitDoneDAC: 1
sConfigError: 0
sRstBusy: 0
sInitDoneADC: 1
sConfigError: 0
sInitDoneRelay: 1
sDataOverflow: 1
Checking DMA Status...
DMA Status Register: 0x0
DMA is running.
DMA is active.
-----------------------------------.
The ADC is indeed overflowing and the DMA status register is initially halted and keeps being 'running' after I started the HLS IP. But I'm not sure this is the expected behavior or not.
Any insights or further recommendations you could provide would be greatly appreciated!
