Configuration Clock on Arty A7

[Fadi]

Hello Everyone, 

Im new to all this so bear with me please.

I am studying the schematic of Arty A7 100T board and confused about the connection of CCLK and EMCCLK pins. I read in documentation that EMCCLK pin is used to attach an external clock source to speed up the configuration process when configuring from QSPI. but in the Arty A7 schematic the EMCCLK pin is connected to QSPI_SCK signal that itself is being generated from FPGA through CCLK pin when its working as a Master device.

kindly if someone can explain all this it'll be a great help. Thanks 

[artvvb]

Hi @Fadi

Both CCLK_0 and EMCCLK are connected to the QSPI SCK pin. E9 is used during boot, while L16 can be used after a bitstream has been programmed in to access Flash without using special primitives. Quoting the manual's QSPI section:

Quote

... on the Arty A7 the SCK signal is routed to an additional general purpose pin that can be accessed after configuration (see Figure below). This allows access to this pin without having to instantiate the special FPGA primitive called STARTUPE2.

Thanks,

Arthur

[Fadi]

so you mean to say that after configuration if clock is required we can configure L16 pin as output and use it instead as CCLK_0 cant be accessed directly.

[artvvb]

Yes, that's correct.