chclau

Several VHDL code examples with source code and simulation waveform. Also, at the footer of each example, there is a link to download both the model source and testbench files from GitHub.
The full list is here, and this are the individual code examples:
AXI-Lite register bank
Generic register with load
Binary to seven-segment decoder
Generic demultiplexer and decoder
Generic down-counter
Modulo counter
Parallel to serial converter

https://fpgaer.tech/?p=533 - Part 1, what is an arbiter?
https://fpgaer.tech/?p=542 - Part 2, implementing and testing a fixed-priority arbiter
https://fpgaer.tech/?p=622 - Part 3, Round-robin VHDL arbiter, code and testbench

https://fpgaer.tech/?p=447

A1) You don't need a slave connected for the master to exercise the I2C outputs
A2) Did you check that the address range you defined in the interconnect is the same as it is expected by your .c example code?
A3) You don't need additional HW (Verilog or other) code for this to work. I guess the cause of the problem can be on the address range.
As a proposition for you to debug, try to make a simpler task to check that your system is alive. For example, blink some LEDs from your PS processor using Vitis. Once you have succeeded doing that, go back to more complex problems.
As an additional point, you need to learn how to debug. How to debug the SW using the VITIS, and how to debug HW usign testbenches and ILA (Integrated Logic Analyzer). If you can't see where your problem is, it is difficult to solve it.

https://fpgaer.tech/?p=465
Magellan HW monitor for Basys 3 board
Access register bank for reading/writing via JTAG to AXI adapter.
Can also monitor register values via the board seven-segment display (register address is selected through SW0-3)
 

Several VHDL code examples with source code and simulation waveform. Also, at the footer of each example, there is a link to download both the model source and testbench files from GitHub.
The full list is here, and this are the individual code examples:
AXI-Lite register bank
Generic register with load
Binary to seven-segment decoder
Generic demultiplexer and decoder
Generic down-counter
Modulo counter
Parallel to serial converter

Thank you all for your replies, I realised I had not uncommented the first get_ports clk line in the xdc file and now it generates the bitstream!  
About the board being installed warning, when i create a new project, this is what i see when selecting the board, is this correct?
I didn't install vitis since i didn't have enough space and only plan to do hardware designs for now, does this have anything to do with the warning?

Thank you!

You have to understand the format of the .xdc file that instructs the compiler how to interpret the pins. The error message is above your source file so we cannot see everything but one thing I noticed is that you used a "led" signal. The Basys 3 has several leds so they are numbered. Go through the tutorial again, you should replace on your .xdc files all mentions from "LED[0]" to "led". I don't know the name of t he clock pin you used but I hope you understand the logic of whay you have to do from my answer