I want to get an analog signal by processing the digital signal output from the zybo through the i2c.
(I will use tca9548a and mcp4725 for DAC)
To do this, I want to make sure that there is a digital signal from zybo-z7 through i2c.
I made a block design using Axi_iic IP, and set the SCL to JE1(V12) and the SDA to JE2(W16) through the constraints file. After that, I ran the ‘xiic_selfftest_example.c’ code through Vitis.
After connecting jumper wires to JE1 and JE2, the oscilloscope measured the voltage and found that both(SCL, SDA) output 3.3V. However, there is no change from 3.3V (High) to 0V (Low).
I know that i2c communication starts when SDA becomes low, but the project I designed is not.
Q1) Is i2c communication not started because the i2c slave device(ex. tca9548a) is not connected to zybo?
If this is correct, how do I specify the Slave address? (Is it designated by the C code in vitis?)
Q2) Do I need to run code other than " xiic_selfftest_example.c " to start i2c communication?
(Is there an example code to start i2c communication?)
Q3) I designed using only block design, but is it necessary to create a separate Verilog code for i2c communication?
Q4) I set the pull-up resistance on the FPGA through the constraints file, is this not enough? (Do I have to connect a separate resistance?)
Can this be the reason that output is not a digital signal?
Ps: I purchased a Pmod (Pmod AD2, Pmod CMPS2) using i2c bus to learn i2c communication. Can I understand i2c communication by practicing how to use these pmod?
I am attaching the Block design, constraints code, and oscilloscope measurement results of JE1(SCL) pin.
Question
suung33
Hello, I'm a student studying about FPGA.
I want to get an analog signal by processing the digital signal output from the zybo through the i2c.
(I will use tca9548a and mcp4725 for DAC)
To do this, I want to make sure that there is a digital signal from zybo-z7 through i2c.
I made a block design using Axi_iic IP, and set the SCL to JE1(V12) and the SDA to JE2(W16) through the constraints file. After that, I ran the ‘xiic_selfftest_example.c’ code through Vitis.
After connecting jumper wires to JE1 and JE2, the oscilloscope measured the voltage and found that both(SCL, SDA) output 3.3V. However, there is no change from 3.3V (High) to 0V (Low).
I know that i2c communication starts when SDA becomes low, but the project I designed is not.
Q1) Is i2c communication not started because the i2c slave device(ex. tca9548a) is not connected to zybo?
If this is correct, how do I specify the Slave address? (Is it designated by the C code in vitis?)
Q2) Do I need to run code other than " xiic_selfftest_example.c " to start i2c communication?
(Is there an example code to start i2c communication?)
Q3) I designed using only block design, but is it necessary to create a separate Verilog code for i2c communication?
Q4) I set the pull-up resistance on the FPGA through the constraints file, is this not enough? (Do I have to connect a separate resistance?)
Can this be the reason that output is not a digital signal?
Ps: I purchased a Pmod (Pmod AD2, Pmod CMPS2) using i2c bus to learn i2c communication. Can I understand i2c communication by practicing how to use these pmod?
I am attaching the Block design, constraints code, and oscilloscope measurement results of JE1(SCL) pin.
Thanks.
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