Jump to content
  • 0

zybo z7-10 I2C master


suung33

Question

Hello, I'm a student studying about FPGA.

I want to get an analog signal by processing the digital signal output from the zybo through the i2c.
(I will use tca9548a and mcp4725 for DAC)

To do this, I want to make sure that there is a digital signal from zybo-z7 through i2c.
I made a block design using Axi_iic IP, and set the SCL to JE1(V12) and the SDA to JE2(W16) through the constraints file. After that, I ran the ‘xiic_selfftest_example.c’ code through Vitis.

 

After connecting jumper wires to JE1 and JE2, the oscilloscope measured the voltage and found that both(SCL, SDA) output 3.3V. However, there is no change from 3.3V (High) to 0V (Low).
I know that i2c communication starts when SDA becomes low, but the project I designed is not.

 

Q1) Is i2c communication not started because the i2c slave device(ex. tca9548a) is not connected to zybo?
If this is correct, how do I specify the Slave address? (Is it designated by the C code in vitis?)

 

Q2) Do I need to run code other than " xiic_selfftest_example.c " to start i2c communication?
(Is there an example code to start i2c communication?)

 

Q3) I designed using only block design, but is it necessary to create a separate Verilog code for i2c communication?

 

Q4) I set the pull-up resistance on the FPGA through the constraints file, is this not enough? (Do I have to connect a separate resistance?)
Can this be the reason that output is not a digital signal?

 

Ps: I purchased a Pmod (Pmod AD2, Pmod CMPS2) using i2c bus to learn i2c communication. Can I understand i2c communication by practicing how to use these pmod?

 

I am attaching the Block design, constraints code, and oscilloscope measurement results of JE1(SCL) pin.

 

Thanks.

Block design.png

constraints file.png

oscilloscope result.jpg

Link to comment
Share on other sites

1 answer to this question

Recommended Posts

  • 0

A1) You don't need a slave connected for the master to exercise the I2C outputs

A2) Did you check that the address range you defined in the interconnect is the same as it is expected by your .c example code?

A3) You don't need additional HW (Verilog or other) code for this to work. I guess the cause of the problem can be on the address range.

As a proposition for you to debug, try to make a simpler task to check that your system is alive. For example, blink some LEDs from your PS processor using Vitis. Once you have succeeded doing that, go back to more complex problems.

As an additional point, you need to learn how to debug. How to debug the SW using the VITIS, and how to debug HW usign testbenches and ILA (Integrated Logic Analyzer). If you can't see where your problem is, it is difficult to solve it.

Link to comment
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now
×
×
  • Create New...