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Bitstream Generation failed. Vivado 2020.1


Anthocyanina

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I'm following the blink LED tutorial from here, for the Basys 3 board. I've selected the board when creating the project. https://digilent.com/reference/programmable-logic/guides/getting-started-with-vivado

At the Bitstream generation part, I'm getting this error:

image.thumb.png.371b65038922d1fc36ea40853e367786.png

Searching for this on the forum led me to this other post, which has a critical warning similar to what I'm getting but it has no answers. Could anyone help with this?

 

Thank you!

 

 

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Take a look at the errors it gives you at the bottom tab of the interface. This should have the reasons why the bitstream generation failed.

 

It looks like you didn't assign non-default pins in your project. Even if the "default" setting is the one you want, you need to manually assign the pin I/O Standard in the xdc file, or in the pin planner.

 

~Kvass

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You have to understand the format of the .xdc file that instructs the compiler how to interpret the pins. The error message is above your source file so we cannot see everything but one thing I noticed is that you used a "led" signal. The Basys 3 has several leds so they are numbered. Go through the tutorial again, you should replace on your .xdc files all mentions from "LED[0]" to "led". I don't know the name of t he clock pin you used but I hope you understand the logic of whay you have to do from my answer

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Hi @Anthocyanina,

@Kvass and @chclau have correctly addressed the .xdc pin name discrepancy that is giving you the error (Vivado, wisely, is very picky about making sure the names of pins match as intended, capitalization and all, rather than trying to make some interpretive guess about what you are wanting).

The critical warning about the board part definition is indicative that you you did not install (and then select) the Digilent board files (usually you have to install them with Vivado closed so it can properly detect them, and then you can select the Basys 3 board itself during the initial project creation rather than the Artix 7 35T FPGA component); the board files themselves aren't necessary for HDL designs, but are helpful if you do block design work and want to use Digilent's pre-configured materials for some of the on-board components.

Thanks,
JColvin

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Thank you all for your replies, I realised I had not uncommented the first get_ports clk line in the xdc file and now it generates the bitstream! image.png.059efa898a084b8442c5eb97031eb0be.png 

About the board being installed warning, when i create a new project, this is what i see when selecting the board, is this correct?

I didn't install vitis since i didn't have enough space and only plan to do hardware designs for now, does this have anything to do with the warning?

boards.thumb.png.59ff0c7169e603a7ed2a139adfe9be42.png

Thank you!

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Hi @Anthocyanina,

That seems to be the correct board selection based on the Xilinx Board Store (it seems to be file version 1.1 rather than version 1.2 like Digilent has on our own board files which we supplied to Xilinx (https://github.com/Digilent/vivado-boards/tree/master/new/board_files/basys3/C.0), but regardless that shouldn't have brought up this warning, though you should be able to safely proceed with the HDL projects in the meantime.

I don't think leaving out Vitis should cause this issue, at least that I am aware of.

I know there are some files within the Xilinx installation that can be safely deleted to save you more space on your hard drive since that is a concern for you; the place I would be looking in the:

Quote

Xilinx:/Vivado/2020.1/data/parts/xilinx/devint/vault

folder since a lot of Versal parts get installed in there (even if the box during installation is left unchecked) which are quite large. I safely deleted those parts from the installation as well as other parts that I do not intend to use from the Xilinx:/Vivado/2020.1data/parts/xilinx/ folder for various artix7, kintex7, virtext7, zynq, etc parts that I know I do not need. But the biggest culprit was for sure the Versal parts and the zynquplus folder that saved me several gigabytes of space (and the multiple copies of the multi gigabyte identical EULA that is included in various parts of the file structure).

Thanks,
JColvin

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Hi @Anthocyanina,

I personally deleted the versal folder that was in the file location that I referenced; I haven't personally experienced any detriment in my Vivado experience (depending on what devices you have installed, you might see some sort of Warning that Vivado can't find the parts for Versal devices), but maybe your experience will be different. There's always the backup option of uninstalling and then reinstalling Vivado if something goes wrong.

This goes outside the scope of the Digilent Forum at large and is purely JColvin's recommendation (not Digilent endorsed or anything like that) but I've personally used an application call WinDirStat, https://windirstat.net/, to analyze and find where and how my hard drive/SSD space is being taken up by different files.

Thanks,
JColvin

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