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engrpetero

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Topics posted by engrpetero

  1.  

    Question: Vivado/Vitis new AXI peripheral - at wit's end 1 2

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 29 answers
  2.  

    Question: Multiple Displays

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 20 answers
  3.  

    Question: XADC Example with Vivado block diagram?

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 19 answers
  4.  

    Question: Zybo Z7 - UART over one of the PMOD ports example

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 18 answers
  5.  

    Question: Zynq SPI0 - EMIO

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 16 answers
  6.  

    Question: Vivado IP board change/Retarget IP

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 12 answers
  7.  

    Question: Multiple PS Uart Interrupts not seen

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 12 answers
  8.  

    Question: PS GPIO - baremetal

    By engrpetero, in FPGA

    • Has best answer
    • 0 votes
    • 12 answers
  9.  

    Question: Vitis hangs when creating platform

    By engrpetero, in FPGA

    • Has best answer
    • 0 votes
    • 8 answers
  10.  

    Question: Digital Discovery Scripting

    By engrpetero, in Test and Measurement

    • Awaiting best answer
      
    • 0 votes
    • 7 answers
  11.  

    Question: Vivado upgrade woes

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 6 answers
  12.  

    Question: AXI Peripheral - User Logic testing

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 5 answers
  13.  

    Question: ZYboZ7 XADC example - ref to xadc_wiz_0/myxadc?

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 5 answers
  14.  

    Question: Digital Discovery - Zybo interaction

    By engrpetero, in Test and Measurement

    • Awaiting best answer
    • 0 votes
    • 5 answers
  15.  

    Question: Force custom IP ports to update?

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 5 answers
  16.  

    Question: AXI Peripheral concept question

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 4 answers
  17.  

    Question: Documentation sources and SDK

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 4 answers
  18.  

    Question: Digital Discovery - Step Back

    By engrpetero, in Test and Measurement

    • Awaiting best answer
    • 0 votes
    • 4 answers
  19.  

    Question: More on that pesky MIO second UART

    By engrpetero, in FPGA

    • Has best answer
    • 0 votes
    • 3 answers
  20.  

    Question: putting pieces together and Vivado icons

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 2 answers
  21.  

    Question: Digilent board files - edits

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 2 answers
  22.  

    Question: Digital Discovery - Script Question 2

    By engrpetero, in Test and Measurement

    • Awaiting best answer
    • 0 votes
    • 2 answers
  23.  

    Question: Zybo Master Constraints file and PMOD port JF?

    By engrpetero, in FPGA

    • Has best answer
    • 0 votes
    • 2 answers
  24.  

    Question: PL Timing analysis

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 2 answers
  25.  

    Question: Zybo Z7 clocks and xscutimer

    By engrpetero, in FPGA

    • Awaiting best answer
    • 0 votes
    • 2 answers
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