It's taken a week for the lightbulb to go off with respect to Vivado board files, particularly the board file for the ZyboZ7. When creating a new design, with this board file as the basis, I've only now realized that when I add a Zynq7 Processing system as IP, the 'default' settings (things enabled, and their 'properties') are always the same. Surely this is coming from the board file (well, files since there are 3 of them) for if I just create a design with the same FPGA as found on the Zybo, the Zynq7 Processing system IP is different.
Assuming this to be right, my question is... In general, it seems that at if I screw around with IO Peripherals, I'm likely to make things not work with this board, right?
For example, based on the picture below (which contains the 'defaults')...
If I change the UART1 MIO from the default (MIO 48...49) to something else, then since the MIO 48 and 49 pins are what's actually physically routed to the FTDI chip and then the USB/UART connector, I wouldn't be able to communicate with the UART over the Zybo connector.
Same would apply to the GPIO pins next in the MIO configuration page?
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engrpetero
Still drinking from the firehose...
It's taken a week for the lightbulb to go off with respect to Vivado board files, particularly the board file for the ZyboZ7. When creating a new design, with this board file as the basis, I've only now realized that when I add a Zynq7 Processing system as IP, the 'default' settings (things enabled, and their 'properties') are always the same. Surely this is coming from the board file (well, files since there are 3 of them) for if I just create a design with the same FPGA as found on the Zybo, the Zynq7 Processing system IP is different.
Assuming this to be right, my question is... In general, it seems that at if I screw around with IO Peripherals, I'm likely to make things not work with this board, right?
For example, based on the picture below (which contains the 'defaults')...
If I change the UART1 MIO from the default (MIO 48...49) to something else, then since the MIO 48 and 49 pins are what's actually physically routed to the FTDI chip and then the USB/UART connector, I wouldn't be able to communicate with the UART over the Zybo connector.
Same would apply to the GPIO pins next in the MIO configuration page?
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