PL Timing analysis

[engrpetero]

I've completed a few designs and feel like I'm making a lot of progress with both the PL and PS side of the Zynq devices.  Lots more to learn though.  

In Vivado, when I open the implemented design, I can look at the content in the tree but I confess I know very little about what I'm seeing and am unsure how to address concerns (Warnings, Bad Practice, etc.), I see in the 'Violations'.  Can anyone point me to good documentation sources to read to continue learning, please?  

 

[artvvb]

So there's a lot to it. The "UltraFast Design Methodology" document might be a decent thing to go through, as it describes Xilinx's recommended workflow: https://docs.xilinx.com/r/2023.1-English/ug949-vivado-design-methodology/Introduction. That said, the PDF version is well over 300 pages and the document assumes quite a bit of knowledge, though it does link to some summaries in the intro. UG903 also has a lot of info related to timing: https://docs.xilinx.com/r/2023.1-English/ug903-vivado-using-constraints/Introduction. A lot of what I've personally learned has come from clicking around in the tools, googling everything I see (which mostly results in finding various forum threads and answer records), and skimming any pertinent documentation I can find.

[engrpetero]

Thanks for those suggestions, @artvvb.  I've done a good amount of googling and reading various questions/answers.  I'd certainly do well with a stronger base knowledge so your links are appreciated.