putting pieces together and Vivado icons

[engrpetero]

So I continue to make progress with my current project.  I've created several Verilog modules and test benches for them and am happy with the results.  I've got an Axi-Lite peripheral and can write and read to its memory addresses as expected.  Next step is to instantiate some of the mentioned verilog modules in the Axi-Lite peripheral to complete a portion of the design. I have copied the verilog modules with the mentioned designs into the src file of my created IP.

My top level project has a block design with an instance of the mentioned Axi-Lite peripheral.  So I highlight it, then click the 'Edit in IP Packager' menu item to access that design and begin the edits to instantiate content from the modules.  I then add as a Design Source one of the files (ExtConverter) with a design in intend to instantiate in the Axi-Lite peripheral.  I do instantiate one instance of ExtConverter in the peripheral.  My design sources window looks like the picture below.  I don't know what the red question mark icons indicate (but it doesn't seem good). 

I repackage the IP to return to my top level project and after I upgrade the IP, I 'Generate Output Products' and then attempt to synthesize again.  Unfortunately, I am met with Vivado errors (see second pic).  

So my two questions... 1) what do the red question mark icons mean, and 2) why am I getting these errors? 

[artvvb]

The red question mark means that Vivado can't locate the modules in the project's source files. If files containing a module can be found, the filename is typically listed in parentheses next to the module name, if they can't, they get this icon. You may need to add the source files containing the modules to your IP packager project, both in the sources -> design sources view, and to the component XML file's file groups page. The missing modules could also be placed in the same source file as your AXI peripheral, though this isn't usually recommended (one module per file is a common style).

IPs' generated files are split out into their own source sets in the base Vivado project, so you shouldn't need to worry about duplicate names for files or modules.

Thanks,

Arthur

[engrpetero]

Thanks, Arthur.  Adding the files to the File Groups as you suggested fixed the issue and allowed the instantiation and at least got by the initial errors with synthesis (I had already added them to the Sources but that hadn't fixed the problem).  There are other errors - but I can move on to tackling those.  Your help much appreciated.