Clarification regarding AXI Uartlite

[subasheee]

Hi,

I am trying to use AXI Uartlite IP to send some data to COM port of Nexys video board. I went through PG142 and PG155 product guides and figured out the way to initialize different ports of the IP.

The AXI Uartlite is configured as follows.

CLK 1MHz, baud rate 9600, data bits 8

S_AXI_wvalid <= '1';

S_AXI_wstrb <= '1';

S_AXI_awvalid <= '1';

S_AXI_aresetn <= '1';

S_AXI_awaddr <= "0100";

S_AXI_wdata <= "00000000000000000000000001010011";

When I simulate, the TX port output of AXI Uartlite just remains ‘X’ state instead toggling as per S_AXI_wdata. I have simulated upto 4 seconds and ll the values are initialized from the beginning of  simulation.

Am I missing any configuration setting? or anything needs to be carried out to get teh data at TX port ?

Help is much appreciated.

Regards,
Subash

[jpeyron]

Hi @subasheee,

I know that you can use the test bench that vivado makes to simulate the uartlite. Is this the test bench you are using?  Usually when I get X's and I'm pretty sure my hdl and test bench is good then its because I forgot to to give initial values to my signals. Have you looked at the hello world template in sdk after making a block design with the uartlite?

thank you,

Jon

[subasheee]

On 3/24/2018 at 11:59 PM, subasheee said:

S_AXI_awvalid

Hi @jpeyron

Thanks for your reply. Apparently, the s_axi_aresetn pin of AXIuartlite  should be made logic high after few nano seconds. Initially i kept it at high from starting of simulation.

Regards,

Subash

[jpeyron]

Hi @subasheee,

Glad to hear that you were able to get your simulation working.

thank you,

Jon