Stop watch project on Basys 3

[Alex]

I have done this project for an online class. The project is written by Verilog. The clock generator, enable_sr(enable digit) and ssd (seven segment display) modules were provided. My task was to write the top module and counter modules to make a stop watch on the 7 segment display. Originally, the project was implemented in Basys 2. I also used Xilinx ISE Webpack. Now, I modified the project and implemented it on Basys 3. In addition, I used Vivado Webpack instead of ISE. I have also written up a getting started guide for Vivado.

http://www.instructables.com/id/How-to-use-Verilog-and-Basys-3-to-do-stop-watch/

[Commanderfranz]

Alex,

Thanks for posting your project! 

Kaitlyn