Device Tree Failure Zybo 2017.2 BSP PetaLinux 2017.3

[jackfrye11]

Hello, I have created a Vivado FPGA design with the provided Zybo board add-on to Vivado from here https://github.com/Digilent/vivado-boards/tree/master/new/board_files/zybo/B.3

I then created  a PetaLinux 2017.3 project with the 2017.2 BSP from here, https://github.com/Digilent/Petalinux-Zybo/releases.

I then ran the PetaLinux command that sources the hardware design:

Quote

petalinux-config --get-hw-description=<path to the hdf file generated by Vivado with Zybo board above>

Finally, I have attempted to build the project but the device tree is failing to build.

Quote

ERROR: device-tree-generation-xilinx+gitAUTOINC+5b21302249-r0 do_compile: Function failed: do_compile (log file is located at /home/jfrye/Developer/Xilinx/PetaLinuxProjects/ZyboPS/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+5b21302249-r0/temp/log.do_compile.12531)
ERROR: Logfile of failure stored in: /home/jfrye/Developer/Xilinx/PetaLinuxProjects/ZyboPS/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+5b21302249-r0/temp/log.do_compile.12531
Log data follows:
| DEBUG: Executing shell function do_compile
| Error: /home/jfrye/Developer/Xilinx/PetaLinuxProjects/ZyboPS/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+5b21302249-r0/system-user.dtsi:53.1-9 Label or path amba_pl not found
| Error: /home/jfrye/Developer/Xilinx/PetaLinuxProjects/ZyboPS/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+5b21302249-r0/system-user.dtsi:75.1-14 Label or path axi_dynclk_0 not found
| Error: /home/jfrye/Developer/Xilinx/PetaLinuxProjects/ZyboPS/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+5b21302249-r0/system-user.dtsi:80.1-12 Label or path axi_vdma_0 not found
| Error: /home/jfrye/Developer/Xilinx/PetaLinuxProjects/ZyboPS/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+5b21302249-r0/system-user.dtsi:83.1-10 Label or path v_tc_out not found
| Error: /home/jfrye/Developer/Xilinx/PetaLinuxProjects/ZyboPS/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+5b21302249-r0/system-user.dtsi:87.1-15 Label or path axi_gpio_hdmi not found
| Error: /home/jfrye/Developer/Xilinx/PetaLinuxProjects/ZyboPS/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+5b21302249-r0/system-user.dtsi:92.1-9 Label or path amba_pl not found
| Error: /home/jfrye/Developer/Xilinx/PetaLinuxProjects/ZyboPS/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+5b21302249-r0/system-user.dtsi:126.1-15 Label or path axi_i2s_adi_0 not found
| Error: /home/jfrye/Developer/Xilinx/PetaLinuxProjects/ZyboPS/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+5b21302249-r0/system-user.dtsi:148.1-14 Label or path axi_gpio_led not found
| Error: /home/jfrye/Developer/Xilinx/PetaLinuxProjects/ZyboPS/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+5b21302249-r0/system-user.dtsi:153.1-17 Label or path axi_gpio_sw_btn not found
| FATAL ERROR: Syntax error parsing input tree
| WARNING: exit code 1 from a shell command.
| ERROR: Function failed: do_compile (log file is located at /home/jfrye/Developer/Xilinx/PetaLinuxProjects/ZyboPS/build/tmp/work/plnx_arm-xilinx-linux-gnueabi/device-tree-generation/xilinx+gitAUTOINC+5b21302249-r0/temp/log.do_compile.12531)

 

I am not sure why this is. I will probably try to install 2017.2 PetaLinux and use the same board design from Vivado 2017.3 and if that doesn't work, move back to Vivado 2017.2 for the hardware.

1. Has anyone else seen this issue?

2. 2017.2 is 2 major releases ago. When is are the BSPs going to be updated?

 

Thanks.

 

[jackfrye11]

Also tried with 2017.2 PetaLinux and failed. Might try with 2017.2 Vivado on hardware and we will see how it goes. then I will go from this example if it fails and see where it breaks: https://github.com/Digilent/Petalinux-Zybo/blob/master/README.md

 

[jpeyron]

Hi @jackfrye11,

I have reached out to a more experience embedded linux engineer about your forum thread.

thank you,

Jon 

[sbobrowicz]

I think your vivado project might be missing some needed IP. The intended design flow is for you to start with this vivado project, and then make modifications as needed:

https://github.com/Digilent/Zybo-base-linux

Looking at the README.md, this is definitely not made clear enough. I will revamp the README.md on the next release and add a section about modifying the vivado design.

Judging from the error, I'm guessing your project doesn't have anything attached to the GP AXI ports of the PS (the auto generated pl.dtsi seems to not even contain an amba_pl node, which I've never seen). The other option would be for you to modify project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi to remove any reference to components not found in your design. You will need to learn a bit about device trees, but if you are digging into embedded linux projects, that is in your future anyways :). 

[jackfrye11]

thats fine. It looked like custom hardware was not part of the workflow, but I wanted to make sure. I have not found any digilent resources that demonstrate how to link custom hardware in the PL with the device tree in the PS. This is simple using the zc706 board I have at work, but with the Zybo, finding resources has been a little more challenging. And yes, I considered manually changing the device tree to match my hardware. This is usually done automatically by petalinux with the --get-hw-description command. When I tried to make a project that way "from scratch" with the Zybo board for Vivado and the bsp for 2017.2, I was not able to boot the produced images. Perhaps I should create another thread addressing that issue.

 

[sbobrowicz]

Good feedback, I'll send it up the chain. What you are asking to do is quite common.

Digilent doesn't currently provide a PS only BSP, which is likely what you were using with the ZC706. That allows a basic flow for creating your design from scratch, but rips out any functionality that requires the PL, such as HDMI output and GPIO. If you attempt to add in any of that functionality on your own, it will be up to you to configure the IP in a way that works with the Linux drivers and to write the device tree to get them to play nice. Given limited resources, Digilent went with providing a single, all inclusive BSP under the premise that it tends to be much easier to rip things out of the vivado projects and device tree than to add them in and get them working. Granted, some additional documentation is called for.

Yea, if they produced different errors then you should probably spin up another thread.

[marc_v3]

8 hours ago, sbobrowicz said:

I think your vivado project might be missing some needed IP. The intended design flow is for you to start with this vivado project, and then make modifications as needed:

https://github.com/Digilent/Zybo-base-linux

Looking at the README.md, this is definitely not made clear enough. I will revamp the README.md on the next release and add a section about modifying the vivado design.

Judging from the error, I'm guessing your project doesn't have anything attached to the GP AXI ports of the PS (the auto generated pl.dtsi seems to not even contain an amba_pl node, which I've never seen). The other option would be for you to modify project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi to remove any reference to components not found in your design. You will need to learn a bit about device trees, but if you are digging into embedded linux projects, that is in your future anyways :). 

I don't see an .xpr file in https://github.com/Digilent/Zybo-base-linux. How do you edit this project's PL?

I am working with jackfrye11 on this project.

[sbobrowicz]

The project generation is scripted for better version control and sharing. See this guide:

https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start

 

[marc_v3]

Thanks, that is just what I needed.

Let me know if I should make a new post for this. I am getting the following errors when running "create_project.tcl"

ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design 'system.bd' is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. 
List of locked IPs: 
system_rgb2dvi_0_0
system_axi_dynclk_0_0

I understand this is because the design was created with an earlier version of Vivado. I tried the solution posted at https://forum.digilentinc.com/topic/4505-zybo-dma-audio-demo-error/#comment-17914

When I go to Tools>Report>Report IP Status, I get the following:

 

"Upgrade Selected" is permanently grayed out, even when the IP is selected. It seems the IP is too out of date and cannot update.

I am using Vivado 2017.2, and the readme on the project says "Created for Vivado 2017.2"

[sbobrowicz]

It looks like you don't have the vivado-library repo. This typically happens if you downloaded the repo using the Download ZIP button on Github, which doesn't include git submodules. Two options: clone the base-linux repo with the following command line:

git clone --recursive https://github.com/Digilent/Zybo-Z7-20-base-linux.git

Or use you project: run the cleanup script in the proj folder, download the vivado-library repo from our github (you can use the Download ZIP button, it doesn't have submodules), and copy the vivado-library folder to the repo folder in your project. then re-run 

I recommend the first option, it will just make things easier in the long run if you use git. Whichever you choose, you should then run create_project.tcl, and you will see that same error again. Upgrade the IPs (it should work this time), and then close Vivado (don't forget to close Vivado). Then run the clean-up script in the proj folder (or just manually delete everything there except the cleanup scripts, release script, and create_project.tcl). Then run the create_project.tcl and all should work.