entity AND_GATE is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end AND_GATE;
architecture Behavioral of AND_GATE is
begin
c<= a AND b;
end Behavioral;
=============
Now, it runs just fine, but for some reason my Basys 3's LED 4 digit display is flickering like crazy, with a faint 8888. Is this a known issue? Am I missing something?
Question
Fancellu
Just some silly hello world code (I'm a super newbie to FPGAs)
Vivado 2017.4, windows 7
xdc as per https://reference.digilentinc.com/learn/programmable-logic/doc/github/digilent-xdc =>
set_property IOSTANDARD LVCMOS33 [get_ports a]
set_property IOSTANDARD LVCMOS33 [get_ports b]
set_property IOSTANDARD LVCMOS33 [get_ports c]
set_property PACKAGE_PIN U16 [get_ports c]
set_property PACKAGE_PIN W19 [get_ports a]
set_property PACKAGE_PIN T17 [get_ports b]
vhdl=>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND_GATE is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end AND_GATE;
architecture Behavioral of AND_GATE is
begin
c<= a AND b;
end Behavioral;
=============
Now, it runs just fine, but for some reason my Basys 3's LED 4 digit display is flickering like crazy, with a faint 8888. Is this a known issue? Am I missing something?
Thanks
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