Jump to content

Search the Community

Showing results for tags 'basys'.

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Test and Measurement
    • Measurement Computing (MCC)
    • Add-on Boards
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions
    • Archived

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 2 results

  1. Hello I am creating a verilog module on the basys 3 board to interface with the Pmod DA3. I have tried running the module with the DA3 connected and wasn't getting any voltage reading. I have my sclk speed at 25Mhz. Below is my current code and screenshots of my test bench and the pmod outputs on an oscilloscope. Any help is appreciated. `timescale 1ns / 1ps module sclk( input clock, input reset, output sclk ); reg[24:0] count = 0; reg sclk = 0; always @ (posedge clock or posedge reset) begin if (reset ==1'b1)begin count <= 0; sclk <= 0; end else begin count <= count + 1; if(count == 1) begin sclk <= ~sclk; count <= 0; end end end endmodule __ `timescale 1ns / 1ps module spi0( input clock, input reset, input send, output sclk0, output reg cs, output reg ldac, output reg din ); reg[15:0] data [3:0]; reg[15:0] count; reg [1:0] sel; sclk sclk_inst ( .clock(clock), .reset(reset), .sclk(sclk0) ); initial begin data[0] = 16'b0101111000010101; data[1] = 16'b1000011111100001; count = 16'd16; cs = 1; sel = 0; end always @ (negedge sclk0 & send == 1)begin if (send == 1)begin if ( count > 0)begin cs = 0; ldac = 0; end if (count == 0)begin cs = 1; ldac = 1; count = 16'd16; end din = data[sel][count-1]; count = count - 1; end end endmodule __ `timescale 1ns / 1ps module spi0_testbench(); reg clock = 0; reg reset = 0; reg send = 0; reg [50:0]counter = 0; reg [16:0] i; wire sclk0; wire cs; wire ldac; wire din; wire[15:0] count; spi0 UUT(clock, reset, send, sclk0, cs, ldac, din); always @ (*)begin #10 if (i >= 127 & i < 129)begin send = 0; end if (i < 127 | i >= 129) begin send = 1; end if (i < 127)begin end end initial begin for (i = 0; i < 1000; i = i + 1)begin clock = ~clock; counter = counter + 1; #1; end end endmodule Green: SCLK Yellow: DIN Blue: CS Pink: LDAC
  2. Totally new to all this. 73 year old grandpa, retired engineer, returning to grad school, microelectronics concentration. Lots of technology catch-up to do. So, starting with VHDL. I must self-teach VHDL and need my first FPGA. Can someone help me understand these 3 possible choices for someone in my position: (1) Basys MX3 PIC32MX, (2) Nexys A7-100T, (3) Zybo Z7. Don't want to buy anything too complex, but I have to get the basics with ability to grow. Many questions about compatibility, accessories, programming... Can you help me get started?
×
×
  • Create New...