Jtag HS3

[Jnadin]

Hi All,

I am having issues using the JTAG HS3 with my PCB that uses zynq 7020 chip. I have tried using it with zc702 and zedboard and these seems to work however plugging the device into my board the device is not found. I am guess there is something I have missed when designing the board. 

I have the lines pulled high to 3V3 which then go to the FPGA. Is there any thing else I need to consider for the PCB to work with this device? 

was anyone able to design a board that had this JTAG working?

Kind Regards,

J. Nadin

[JayWeeks]

Can you attach a sketch of how you wired the connection between the JTAG HS3 and the Zynq 7020? I'm trying to get a better idea of what you've done that's not working. If I can't figure it out I'll forward this to someone who can.

[Jnadin]

I have attached two schematic drawings.

We have recently got the zynq and jtag talking to each other by setting the boot mode to boot directly from JTAG. Also by removing the pull-ups on the jtag lines.

Original the FPGA was configured to boot from NAND. However, seeing as we have not put any data into the NAND nothing was happening.

I think that the QSPI on zedboard and zc702 must have something inside it so when JTAG is detected you can interrupt the boot sequence. Do you know if this is true or not?

Ideally, we would want to be able to keep the NAND boot mode and intercept with the JTAG.

[JayWeeks]

Do you have the JTAG_INIT pin attached to anything?

So I started looking in the JTAG HS3 reference manual (under "Xilinx Zynq-7000 and SoC Support"), and the Zynq-7000 boards need to have their PS_SRST_B pin connected to the SRST pin of the JTAG HS3 through a pull up resistor. It looks to me that SRST is what you've been calling INIT. Does that sound right to you?

If that's the case, I think your JTAG_INIT should be attached to FPGA_INIT_B (and keep the pullup resistor on the JTAG_INIT line).

Unless, of course, you've already done this, in which case I'll forward this to someone who knows these boards better.

[Jnadin]

I have attached the part of the schematic that connects the jtag init to the ps_srst_b pin. 

Looking at the document you linked, I believe I have called the SRST on the JTAG-HS3 as JTAG_INIT however this looks to only be connected to PS_SRST_B on the FPGA which it already is.

Should this connection remain?Should I add a wire from JTAG_INIT to FPGA_INIT_B?

At the moment the FPGA_INIT_B is only connected to a toggle led. Red if not initialised and green if initialised.

[JayWeeks]

Well it looks to me like everything is set up the way it should be, but I'm also seeing a proprietary USB programming circuit in the ZedBoard schematic that may be complicating things. Now, obviously we can't divulge any information about that programming circuit (I don't actually know anything about it myself), but what I'll do is escalate this question to someone higher up so we can get your question answered.

Unfortunately that may take a little while because we're currently on vacation for the 4th of July, but rest assured that we will get back to you.

Thanks for your cooperation!

[sLowe]

Hey Jonathan,

Luckily the zc702 schematic shows the connections and it looks pretty close to what you have. Some things did catch my eye though. I looks like you pull up your signals to 3.3 V instead of VADJ like they do and they actually have a Bidirectional Voltage-Level Translator to change the 3.3 V signals to Vadj as all the signals terminate on Bank 13 (which is a Vadj bank) This would probably cause some problems.

Here is the schematic http://www.xilinx.com/support/documentation/boards_and_kits/zc702_Schematic_xtp185_rev1_0.pdf

The programming circuit is located on page 35 and Bank 13 is on page 4. 

I will keep looking around but hopefully this helps in the meantime!