Hi t all, actually I new to programming, some places may be completely unknown, but a period of time, I need to do some procedures to detect, but appear in the process of the problem is not so easily solved for me, so I want to seek some help. I have designed a system using Artix-7 FPGA on a custom board. The goal is to transfer 32 bit data to an external on-board chip whose data bus is aninoutport. First, a little background:
The external chip is driven by a 100MHz clock which is generated by the FPGA, let's call ito_clk. The FPGA generates this clock through an MMCM in the Memory Interface Generator (MIG IP) using the 200MHz differential system clock. Theo_clkis looped back from the FPGA's output and is given to another ball as an input clock, let's call iti_clk.
The external chip receives theo_clkand sees data on this clock's rising edge. However, when the external chip sends data back to FPGA, the FPGA sees this data on the looped backi_clk. The idea behind doing so is that we can treat communications as source synchronous, in both the directions (remember, it is aninoutport). Something like below:
FPGA --> EC is synchronous to FPGA because FPGA generates clock
EC --> FPGA is synchronous to EC because FPGA gets external clock (virtually from EC)
To constrain this design, I have used thei_clkto set input delays on theio_dataand have used theo_clkto constrain output on the sameio_databus. I have made sure I am using a forwarded clock (create_generated_clock)(using the ODDR2) for theset_output_delayconstraint.
The system seems to work properly when I run it on hardware, but I still have some doubts because I am still an amateur FPGA developer and this is my first big FPGA design.
My questions are:
Have I designed a good system?
Is it correct to treat the communication from EC http://www.kynix.com/Detail/390575/EC.html --> FPGA as source synchronous? (The other direction is source sync because FPGA is providing clock, if I am not wrong.!)
Question
chuchang
Hi t all, actually I new to programming, some places may be completely unknown, but a period of time, I need to do some procedures to detect, but appear in the process of the problem is not so easily solved for me, so I want to seek some help. I have designed a system using Artix-7 FPGA on a custom board. The goal is to transfer 32 bit data to an external on-board chip whose data bus is an
inout
port. First, a little background:The external chip is driven by a 100MHz clock which is generated by the FPGA, let's call it
o_clk
. The FPGA generates this clock through an MMCM in the Memory Interface Generator (MIG IP) using the 200MHz differential system clock. Theo_clk
is looped back from the FPGA's output and is given to another ball as an input clock, let's call iti_clk
.The external chip receives the
o_clk
and sees data on this clock's rising edge. However, when the external chip sends data back to FPGA, the FPGA sees this data on the looped backi_clk
. The idea behind doing so is that we can treat communications as source synchronous, in both the directions (remember, it is aninout
port). Something like below:To constrain this design, I have used the
i_clk
to set input delays on theio_data
and have used theo_clk
to constrain output on the sameio_data
bus. I have made sure I am using a forwarded clock (create_generated_clock
)(using the ODDR2) for theset_output_delay
constraint.Here are my constraints:
The system seems to work properly when I run it on hardware, but I still have some doubts because I am still an amateur FPGA developer and this is my first big FPGA design.
My questions are:
Many thanks!
Link to comment
Share on other sites
5 answers to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.