Vivado not routing nets

[newkid_old]

Hello all,

    I'm new to the FPGA programming field.  I have a project that I've made a serial to parallel converter.  I have the Arty board and have been able to implement a MicroBlaze processor along with a UART.  I have created an AXI block IP and instantiated my converter.  There are three inputs to this converter that need brought out so I can interface to my data source but only one of them is being routed by Vivado's Implementation tool.  Attached are my project files one for my AXI arch and one for the AXI imp and for my VHDL program.  Any help is greatly appreciated.  The signals are BDX and BFSX.  The signal it did route is the BLCKX (clock).

12bit_ADC_DDR.vhd

DDR_arch.vhd

DDR_inst.vhd

[newkid_old]

Happy to:

Spoiler

 

*** Running vivado
    with args -log ADC_DDR_v1_0.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source ADC_DDR_v1_0.tcl -notrace

****** Vivado v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:09 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source ADC_DDR_v1_0.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 51 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.2
INFO: [Device 21-403] Loading part xc7a35ticsg324-1L
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 520.609 ; gain = 248.035
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
Running DRC as a precondition to command opt_design

Starting DRC Task
Command: report_drc (run_mandatory_drcs) for: opt_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.619 . Memory (MB): peak = 527.742 ; gain = 7.133
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: b5330850

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1015.500 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: b5330850

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1015.500 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 5a57f414

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1015.500 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 5a57f414

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1015.500 ; gain = 0.000
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 5a57f414

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1015.500 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1015.500 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 5a57f414

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1015.500 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation

Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 1 BRAM(s) out of a total of 1 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 2
Ending PowerOpt Patch Enables Task | Checksum: af2413e8

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1029.676 ; gain = 0.000
Ending Power Optimization Task | Checksum: af2413e8

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.844 . Memory (MB): peak = 1029.676 ; gain = 14.176
26 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1029.676 ; gain = 509.066
INFO: [Common 17-1381] The checkpoint 'c:/Users/alienware/Documents/LocalProjects/ip_repo/edit_ADC_DDR_v1_0.runs/impl_1/ADC_DDR_v1_0_opt.dcp' has been generated.
Command: report_drc -file ADC_DDR_v1_0_drc_opted.rpt
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file c:/Users/alienware/Documents/LocalProjects/ip_repo/edit_ADC_DDR_v1_0.runs/impl_1/ADC_DDR_v1_0_drc_opted.rpt.
report_drc completed successfully
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
Command: report_drc (run_mandatory_drcs) for: incr_eco_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
Command: report_drc (run_mandatory_drcs) for: placer_checks
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[10] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[6]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[11] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[7]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[4] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[0]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[5] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[1]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[6] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[2]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[7] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[3]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[8] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[4]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[9] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[5]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 8 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1029.676 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 144e041a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1029.676 ; gain = 0.000
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1029.676 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
ERROR: [Place 30-69] Instance s00_axi_BDX_IBUF_inst (IBUF) is unplaced after IO placer
ERROR: [Place 30-69] Instance s00_axi_BFSX_IBUF_inst (IBUF) is unplaced after IO placer
INFO: [Timing 38-35] Done setting XDC timing constraints.
ERROR: [Place 30-378] Input pin of input buffer s00_axi_BDX_IBUF_inst has an illegal connection to a logic constant value.
ERROR: [Place 30-378] Input pin of input buffer s00_axi_BFSX_IBUF_inst has an illegal connection to a logic constant value.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8930c1f3

Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.870 . Memory (MB): peak = 1029.676 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 8930c1f3

Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.870 . Memory (MB): peak = 1029.676 ; gain = 0.000
ERROR: [Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 8930c1f3

Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.872 . Memory (MB): peak = 1029.676 ; gain = 0.000
41 Infos, 9 Warnings, 0 Critical Warnings and 6 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Thu Oct 26 16:56:27 2017...

*** Running vivado
    with args -log ADC_DDR_v1_0.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source ADC_DDR_v1_0.tcl -notrace

****** Vivado v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:09 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source ADC_DDR_v1_0.tcl -notrace
Command: open_checkpoint ADC_DDR_v1_0_opt.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 228.563 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 51 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.2
INFO: [Device 21-403] Loading part xc7a35ticsg324-1L
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Project 1-604] Checkpoint was created with Vivado v2017.2 (64-bit) build 1909853
open_checkpoint: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 517.238 ; gain = 295.660
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
Command: report_drc (run_mandatory_drcs) for: incr_eco_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
Command: report_drc (run_mandatory_drcs) for: placer_checks
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[10] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[6]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[11] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[7]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[4] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[0]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[5] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[1]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[6] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[2]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[7] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[3]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[8] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[4]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
WARNING: [DRC REQP-1840] RAMB18 async control check: The RAMB18E1 ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg has an input control pin ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/RAMD8_reg/ADDRBWRADDR[9] (net: ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr[5]) which is driven by a register (ADC_DDR_v1_0_S00_AXI_inst/ADC_DDR/rdRAMAddr_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 8 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 528.188 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 144e041a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 528.188 ; gain = 0.000
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1019.738 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
ERROR: [Place 30-69] Instance s00_axi_BDX_IBUF_inst (IBUF) is unplaced after IO placer
ERROR: [Place 30-69] Instance s00_axi_BFSX_IBUF_inst (IBUF) is unplaced after IO placer
ERROR: [Place 30-378] Input pin of input buffer s00_axi_BDX_IBUF_inst has an illegal connection to a logic constant value.
ERROR: [Place 30-378] Input pin of input buffer s00_axi_BFSX_IBUF_inst has an illegal connection to a logic constant value.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8930c1f3

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1019.738 ; gain = 491.551
Phase 1 Placer Initialization | Checksum: 8930c1f3

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1019.738 ; gain = 491.551
ERROR: [Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 8930c1f3

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1019.738 ; gain = 491.551
18 Infos, 8 Warnings, 0 Critical Warnings and 6 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Fri Oct 27 13:51:19 2017...

 

 

[cjferes]

Hi @newkid_old, 

I'm aiming to do something very similar with an Arty A7 and a similar ADC (that has the same LVDS specs as the TI3423). Could you elaborate on how you connected the termination resistors in the breadboard (connection schematic)? Also, any additional comments on the difficulty of the project will be highly appreciated!

Cheers,

[JColvin]

Thank you for sharing what you found!

[newkid_old]

I wanted to add this post(rather a long time I know) that I have found a solution to my problem.  My original intent was to read, using LVDS, a TI3423 development board from the Digilient Arty board.  Utilizing the PMOD header I was able to connect and read values from the ADC.  Here are the details so that anyone wanting to do the same thing can benefit from my journey through Xilinx hell.  Using Xilinx Vivado I used a SelectIO IP block.  I then set the input to DDR and 2 lanes at 6 bits per lane and changed the input points to differential LVDS25.  Since the bank is 3.3Vdc the differential input voltage can be seen on the inputs as long as you use 50ohm resistors across the P/N pairs.  I used a small bread board where my resistors reside.  The key to the data was the frame clock which frames the data.  Xilinx does not mention how to use this clock and only by extensive searching their forums did I find a guru who states the frame clock can be used on the div_clk_in.  On the SelectIO block IP under the clocks tab you have to change the clock to internal which will enable the div_clk_in input.  This is where you land the frame clock.  The SelectIO block expects differential inputs for the data but only wants single ended inputs for the clock and the frame.  I had to place Utility Buffers under the Base IP catalog to bring in differential inputs from the ADC.  To read the data I used the Microblaze uC, uart and 2 axi gpio ip blocks.  I monitor the the frame clock and when it changes states I read the 12 bit word and transfer it out over uart. 

Cheers,

Curt

[jpeyron]

Hi @newkid_old,

The 1 Mhz should work without an issue.

cheers,

Jon 

[newkid_old]

For my test on my prototype board 1 Mhz is my target speed.

[jpeyron]

Hi @newkid_old,

We have not used the IO planner. We would suggest to try using Make External and an XDC instead. Also, what frequency are you trying to use the high speed pmod ports at? Here is a forum post talking about the high speed pmod ports for the arty.

cheers,

Jon

[newkid_old]

Thanks for your help in finding the cause.  Any ideas how I can constrain these signals so that they can make it from the elaborated design to the implemented design?  Since I'm testing this out on an Arty board, my plan was / is to bring these 3 inputs to the PMOD B header of that board(document states its high speed).  In the IO planner I've assigned these signals to package pins but still get the same error.

 

Thanks,

Curt

[jpeyron]

Hi @newkid_old,

A co-worker and I think that the issue is the "illegal connection to a logic constant value" errors. We think that BDX is unconstrained or something, leading it to take a constant 0 outside of the scope of the code that has been provided.

thank you,

Jon

[jpeyron]

Hi @newkid_old,

Could you copy-paste the log output after implementation fails to a text file and post it? This is the easiest way to figure out what your critical warnings are.

thank you,

Jon

[newkid_old]

Here is the screen shots I took of the elaboration.  1. is the over all design. 2. is the inside my IP block highlighting my signal that gets destroyed once it hits the implement stage and 3. Is the second signal that gets destroyed.  I have done more tinkering to see what will work on my code and I've added this:

attribute equivalent_register_removal: string;   
attribute equivalent_register_removal of BDX : signal is "no";
attribute equivalent_register_removal of BFSX : signal is "no";
attribute dont_touch:string;
attribute dont_touch of BDX :signal is "true";
attribute dont_touch of BFSX :signal is "true";

 

Now my synthesis will add an IBUF to my two signals and implementation gives me an error of which I've added a screen shot:

[jpeyron]

Hi @newkid_old,

Could you review the elaborated design and post screen shots of the generated schematic?

cheers,

Jon

[newkid_old]

Here's an update to my situation.  I added a KEEP attribute to my VHDL code after reading about nets not being routed on fpgadeveloper.net.  This addition allowed my net to be routed from my outside port to the edge of my block IP.  Inside the block IP it is routed no where else.  This is only true in the schematic generated by the synthesis tool.  In the implement tool it gives the same results where it shows my ports but no routing.  Does this information help?

[jpeyron]

Hi @newkid_old,

A co-worker and I looked through your code today and was not able to see the issue. I would suggest to simulate the project. This should allow you find the issue and help you resolve it.

cheers,

Jon

[Tickstart]

This forum was your Gate into the Field of Programmables, am Array't?

[newkid_old]

Hi jpeyron,

   Thanks for the pointer to your working IP.  After looking at it I'm pretty sure I did the same thing except I changed the port names to something slightly different so I could track it better in the process.  I have a feeling that the two nets not be routed are a function of some setting I haven't read about.  The odd thing is that synthesis and implementation both state they have done a successful job.  I'm attaching the two pictures of the schematic that is generated by the implementation process.  You can see my two ports but but nothing routed from them into my core, but the BCLKX signal gets buffered and routed.

[jpeyron]

Hi @newkid_old,

I can spend some more time tomorrow looking at your code. I would also suggest to look at this forum. At the bottom there is a working custom IP done in VHDL that should be a good basic reference.

cheers,

Jon