arty7 Generating project failed

[kriob]

Hello,

I'm trying to build this demo:
https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-hdmi-demo/start

and I have error while generating project (after run in console "source ./create_project.tcl")

WARNING: [IP_Flow 19-2406] Cannot identify part xc7k325tffg900-2
ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART'

Please help
Any idea why it happens?

I have:
Windows 8.1
Vivado 2016.4 HLx WebPACK

[D@n]

@kriob,

I'm not sure why it happened, but you are getting an error that indicates that Vivado is trying to build your design for a different board.  IIRC, the xc7k325... is a fairly high powered Kintex part--not at all the Zynq found within the Arty Z7.

You might wish to recheck your configuration (board support) files, to make sure you selected the right board when you started.

Dan

[kriob]

Waird, becouse that demo I use, look like dedicated to Arty Z7 board. What's more in tcl script there isn't such part k325tffg900-2
but there are these lines

set part "xc7z020clg400-1"
set brd_part "digilentinc.com:arty-z7-20:part0:1.0"

To save disc space I installed only packages for Artix-7 and Zynq.

Should I modify tcl script? If so, how?

[jpeyron]

Hi @kriob,

I was just able to get the project to fully generate a bitstream. The HDMI-out project has some known issues in sdk that we are aware of but you should be able to get the project to load into vivado 2016.4 and generate a bitstream, If you make a generic project in vivado 2016.4 are you able to see the arty-z7-20 board? When you installed the board files it should include the arty-z7-20 folder. I have attached screen shots.

cheers,

Jon

[damn-dirty-ape]

I'm having the same issue using Vivado 2017.2.  After running create_project.tcl, if I go to Tools -> Settings I can see that the generated project device is the Arty Z7-20, but when I attempt to run "update-ip-catalog -rebuild" it fails with the following error:

WARNING: [IP_Flow 19-2406] Cannot identify part xc7k325tffg900-2
ERROR: [IP_Flow 19-2232] Current project options are not valid, cannot get 'PROJECT_PARAM.PART'

Any help would be great!

 

Quick Update:

I commented the line 'update_ip_catalog -rebuild' in create_project.tcl, and then I was able to see the block design for the project.  Running "upgrade_ip [get_ips *]" fixed a lot of the problems, but there are still issues with the following IP: rgb2dvi, dvi2rgb, axi_dynclk. 

[jpeyron]

Hi @damn-dirty-ape,

This project was made and works in Vivado 2016.4. Unfortunately, we do not have the ability to update all our projects/demo's to every version of Vivado. I am downloading Vivado 2017.2 and will see what I can do. I can not guarantee anything thou. 

cheers,

Jon

[kriob]

Hi,

I checked board files and everything was on right place so I install all chip files and it works... almost. Now I have few critical warnings:

[BD 41-51] Could not find bus definition for the interface: TMDS
[BD 41-49] Could not find abstraction definition for the interface: TMDS 

and there is no top level module so implementation doesn't run

[artvvb]

@kriob

The TMDS interface can be found in the HDMI project's /repo/vivado-library/if subdirectory, the IP repository is supposed to be added when create_project is run, but this appears to be a difference between 2016.4 and 2017.2. You can add IP repositories manually through the project settings dialog, if 2017.2 has kept this dialog consistent, then you can go into the IP pane and select Repository Manager.

As for the launch runs error, you will also need to manually create an HDL wrapper for the block design. In the sources tab, right click on the block design and select "Create HDL Wrapper".

EDIT: Whoops, mistook the two of you...

I will be releasing a fixed version of the project on Github within the next few hours...

Hope this helps,

Arthur

[kriob]

Hello,

It took me awhile to learn a little about Vivado and thanks to your help I finally generate bitstream and program FPGA. But it still doesn't run perfectly. The USB terminal works but HDMI doesn't display anything. I suppose it may be caused by few critical warnings I can't fix, like this:

[BD 41-51] Could not find bus definition for the interface: TMDS 

"create_project.tcl" doesn't create TMDS (clk_n, clk_p, data_n [2-0], data_p [2-0]) ports so I do it manually (by "add new port") but the warnings still don't disappear. Is there a better way?

Thanks for any help

[artvvb]

You can try grabbing this repository from our Github. Once it is extracted, the repository can be loaded into Vivado through Project Settings -> IP -> Repository Manager. This contains the same interface definition as the repo subdirectory I mentioned back in July. The same process can also be used to add the repo subdirectory's vivado-library copy to the IP Repositories list.

Note that this is one of the things that the create_project script is trying to do, so if it fails before it manages to do this, then that could explain the problem.

Apologies for the hassle here, versioning can be a pain.

-Arthur

[kriob]

Finally, everything works 
I loaded this repository previously just this time it works

Thanks for all your help. Suddenly I learned a lot through this simple demo