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UART based access to an internal FPGA bus


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Hello everybody!

I just finished a series of posts on zipcpu.com describing how a debugging access can be created out of the serial port to provide access into the internals of an FPGA.  Examples include how you can read or write FPGA block RAM, or even an internal scopeToday's post described how to build a software facility for accessing memory mapped I/O components within your design.  Hence, you can issue read and write commands from your host PC software to access the internals of your design.  In many ways, this design was motivated by requests on the forum asking for help while trying to debug an FFT (as one example).  It's a similar, albeit simpler, debugging component to the one I've used myself for debugging designs.  Indeed, I've used the concept presented to debug flash controllers, block RAM, wishbone bus components, the ZipCPU, the ICAPE configuration interface, and much more.

In addition to the articles on zipcpu.com, you can also find all of the code posted on GitHub and licensed under LGPL--should you wish to try it out yourself, or even modify it for your own design.

Even better, since the design is built of entirely open source components, you can build a Verilator simulation and simulate your entire design, a capability many students have struggled to do with their designs.  Not only that, you can also integrate your own components into the design, while continuing to simulate all of the logic within the design.


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