Xilinx's RAM questions

[Joey Weiland]

Hello, im new on this forum.
Im trying to learn how to use a extern DDR2 RAM that my Virtex 5 have. I honestly dont know the step by step. I do this to learn how to use the FPGA in order to gaining experience for a future proyect. The most difficult module that i used was the Display and works fine.
Im using ISE 14.7
With the DDR2 RAM the only thing i did was creating the file that Core Generator Tool provides after the first configuration.
I had a problem there: i couldnt assign all the ports but i was able to create the file anyway. Now i'm not shure what to do next. I'd apreciate any help that someone can provide or some tip to follow.

Sorry but im a little lost in this subject.

I have a Virtex 5, XC5VLX50T.

Thank you!

 

 

 

[D@n]

@Joey Weiland,

Not sure if this'll help much at all or not, but the OpenArty project Spec contains information about how to generate a DDR3 SDRAM controller, and code for controlling that controller via wishbone bus over a WB-to-AXI bridge.  To get the specifics of the controller, though, I needed to read the board support file(s) for the Arty to get the fine details associated with setting it up.  You should be able to get this sort of information from whoever your board supplier was.

What board are you using?

Dan

[jpeyron]

Hi @Joey Weiland,

Here is a forum thread that might help with your situation.

cheers,

Jon