hamster Posted May 12, 2017 Share Posted May 12, 2017 I used the Nexys2's EPP-like parallel interface on my latest (not all that much) FPGA related project - a software GPS receiver. The FPGA was used to capture the raw one-bit samples form a GPS receiver front end at 5,456 MB/s for 200 seconds, without dropping a single bit. I miss the ease of use and the high bandwidth of the old EPP interface... The FPGA code and the C source to read data from it is at https://github.com/hamsternz/Full_Stack_GPS_Receiver/tree/master/misc Link to comment Share on other sites More sharing options...
zygot Posted May 12, 2017 Share Posted May 12, 2017 Mike, I think that we like to read the same stuff... In particular Andrew Holme's Homemade GPS Receiver is a really interesting project. One thing missing from your projects, especially on your wiki site, is a description of what hardware you are using and how it's all connected. So what's the "GPS receiver front end" referring to? As always I like all of your posts so thanks regards Link to comment Share on other sites More sharing options...
hamster Posted May 13, 2017 Author Share Posted May 13, 2017 I collected 6GB more data today, and took some photos. I'll make a blog / build-log entry over the next few days. It was using the testpoints on the KiwiSDR cape for a beaglebone - http://kiwisdr.com/ Link to comment Share on other sites More sharing options...
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