hamster Posted May 12, 2017 Share Posted May 12, 2017 I used the Nexys2's EPP-like parallel interface on my latest (not all that much) FPGA related project - a software GPS receiver. The FPGA was used to capture the raw one-bit samples form a GPS receiver front end at 5,456 MB/s for 200 seconds, without dropping a single bit. I miss the ease of use and the high bandwidth of the old EPP interface... The FPGA code and the C source to read data from it is at https://github.com/hamsternz/Full_Stack_GPS_Receiver/tree/master/misc Link to comment Share on other sites More sharing options...
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