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how to implement 32 bit fma logic can be implemented on basys 3 kit.

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I think you'll find that doing a fused multiply-add on the Basys-3 is a whole lot easier than the infrastructure you need to get there.  Just to prove it, here's the code you need for a fused multiply-add.  It takes two clocks -- although it might not take two clocks at 100MHz.

module fma(i_clk, i_a, i_b, i_c, o_v);
input	i_clk;
input	[31:0]	i_a, i_b, i_c;
output	reg	[31:0]	o_v;

reg	[63:0]	mpy_result, r_v;
reg	[31:0]	i_c;

always @(posedge i_clk)
begin
mpy_result <= i_a * i_b;
tmp_c <= i_c;
end

always @(posedge i_clk)
r_v <= mpy_result + tmp_c;

assign	o_v = r_v[63:32];

endmodule

But ... somehow ... I don't think that was quite what you needed.    Indeed, I would challenge you to run the above module as is with no modifications.    (It's not impossible, so I won't put it past you, ... but it's certainly not how I would tackle any problems ...)

Care to share anything more about what you are trying to accomplish?

Dan

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1 hour ago, D@n said:

i have codes for fma,

idont know how to use it in basys 3 kit as it contain 16 user pins only

1 hour ago, D@n said:

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Heheh ... see, I knew what you were asking wasn't what you wanted.  Perhaps you realize now that you are going to have to think your project through a little more?

Let's start at the top: where is your data coming from?  Is it coming from a digitizer?  How fast is your data coming in from that digitizer?  How many multiply/accumulates will you need to do per second?  How many multiply accumulates will you need to do on a single piece of incoming data?  (for an FIR filter, that would be the number of taps in the filter ...)  Where will that data be coming from?  Where will it be going to?  and how will you know between now and your solution that you have all the pieces working?

In other words, to solve your problem, you will need to design ...

1. The inputs/outputs for your board.  What data rate will you need?  Can the basys handle that data rate?  Indeed, the basys board can do more multiply accumulates than it can handle data coming in.  You'll need to think this through.
2. The interface between your board and those I/O's.  Some digitizers require SPI interfaces.  While simple, they will take some work to get right.  Other digitizers have other needs.  What will your I/O need?
3. Test-points within your code, so that you can verify that it is doing what you want it to be doing.  If there are five steps to your problem, and the third one is broken, how will you know that it's the third one that's broken and not any of the other four?  Plan this out.
4. How many multiple accumulates will you need to do per second?  Per incoming sample?
5. The Basys-3 has a 100MHz clock.  Will your data be coming in at 100MHz?  Will you then need N multiply and accumulate structures within your FPGA, or do you want one multiply-accumulate structure in your FPGA that's going to handle all of those N multiply and accumulates per incoming data?
6. How will you simulate this?
7. How will you run test benches?  How extensive do your test benches need to be?
8. etc.

These are all questions you will need to figure out answers to, and many of them are interrelated.  For example, you will find that data rate, clock speed, and FPGA resources are all tightly coupled.  Knowing your data rate might significantly impact how many on-board DSP's you can use and more.

Just some thoughts for you to work through,

Dan