I'm migrating my ancient project from the Nexys2 to the Nexys Video, in UCF, the Hirose FX2 signals on the Nexys2 were declared as LVTTL I/O standards, while the FMC signals are declared as LVCMOS in the XDC files provided on the Digilent Resource Center. After doing some researches, I know that LVTTL and LVCMOS differ by their input voltages. In the paragraph of Power Supplies in datasheet of the Nexys Video, il mentions "
An FPGA design can dynamically change the VADJ voltage to suit a certain FMC mezzanine card or application. Care
must be taken to disable the regulator first by bringing "VADJ_EN" low, setting "SET_VADJ(1:0)" and enabling the
regulator again. Please note that for proper voltage levels in digital signals connected to VADJ-powered FPGA banks
(ex. user push-buttons), the correct I/O standard still needs to be set in the design user constraints (XDC or UCF
file). See the schematic and/or the constraints file to determine which signals are in VADJ-powered banks. The
provided master UCF and XDC files assume the default VADJ voltage of 1.2V, declaring LVCMOS12 as the I/O
standard for these signals."
The VADJ power rail requires special attention. It is a programmable voltage rail that powers the FMC mezzanine
connector, user push-buttons, switches, XADC Pmod connector, and the FPGA banks connected to these
peripherals (banks 15, 16).
Dose it mean that if I set the SET_VADJ(1:0) on 11, the VADJ voltage = 3.3V, so the FMC signalss' I/O standards can be set as LVTTL?
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Clarissa
Hello everyone,
I'm migrating my ancient project from the Nexys2 to the Nexys Video, in UCF, the Hirose FX2 signals on the Nexys2 were declared as LVTTL I/O standards, while the FMC signals are declared as LVCMOS in the XDC files provided on the Digilent Resource Center. After doing some researches, I know that LVTTL and LVCMOS differ by their input voltages. In the paragraph of Power Supplies in datasheet of the Nexys Video, il mentions "
An FPGA design can dynamically change the VADJ voltage to suit a certain FMC mezzanine card or application. Care
must be taken to disable the regulator first by bringing "VADJ_EN" low, setting "SET_VADJ(1:0)" and enabling the
regulator again. Please note that for proper voltage levels in digital signals connected to VADJ-powered FPGA banks
(ex. user push-buttons), the correct I/O standard still needs to be set in the design user constraints (XDC or UCF
file). See the schematic and/or the constraints file to determine which signals are in VADJ-powered banks. The
provided master UCF and XDC files assume the default VADJ voltage of 1.2V, declaring LVCMOS12 as the I/O
standard for these signals."
The VADJ power rail requires special attention. It is a programmable voltage rail that powers the FMC mezzanine
connector, user push-buttons, switches, XADC Pmod connector, and the FPGA banks connected to these
peripherals (banks 15, 16).
Dose it mean that if I set the SET_VADJ(1:0) on 11, the VADJ voltage = 3.3V, so the FMC signalss' I/O standards can be set as LVTTL?
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