I'd like to use SRAM to DDR Component in my project. First of all, I want to test the component, the top module is at the bottom.
Just like the top module, I write the ddr three times at three address, and read them after some cycles. However, the read data in board is wrong and random.
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Shaw
Hello,
I am using Xilinx Vivado 2014.3.1
I'd like to use SRAM to DDR Component in my project. First of all, I want to test the component, the top module is at the bottom.
Just like the top module, I write the ddr three times at three address, and read them after some cycles. However, the read data in board is wrong and random.
The result is here:
ram_dq_i ram_dq_o 1st write 1234 0000 2nd write 5678 0000 3rd write 9abc 0000 1st read 1111 1234 2nd read 2222 5678 3rd read 3333 9abc
However, the read data(ram_dq_o) may be change with cycles.
Could someone help me with this issue?
Thanks
test_ddr.v
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