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Simulating the Digilent SRAM to DDR component




I am attempting to simulate the SRAM to DDR component https://reference.digilentinc.com/nexys4-ddr:sram

When I run ISIM it stops immediately with the error:  ERROR: at 0 fs: Signal phy_dout index is out of bound , which is coming from somewhere in the MIG files.

My question is, has anyone successfully simulated this module in the past?  Any suggestions on this issue? 

(FYI my own project is here:  https://github.com/Anding/Nexys4-DDR-testing)

Many thanks,

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Thank you JColvin.   I made some progress and the conclusions are

1.  Design entry language must be set to Verilog

2.  After that change, issue the clean up project files command

3.  Regenerate the MIG core

With these changes ISE will commence simulation.  However as MIG has more than 50,000 lines of code it is beyond the webpack limit for ISE and so the simulation becomes disabled.  I've migrated the project to Vivado which has no such simulation limitation and it currently simulates.

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