Two channels from AD1

[Notarobot]

Hi to all,

I was successful in creating working project on Zybo board acquiring voltage using Pmod AD1. It is relatively simple.

However the goal is to utilize both channels of the AD1 Pmod. For this I am looking for guidance from experts and community.

I might be wrong but it seems that I need to create the second instance of Pmod in Vivado but how do I address the second channel pin D1 and how to initialize the second device.

Thank you in advance for any clue

I forget to mention that Pmod AD1 definitions were copied from the Digilent vivado-library-master.

Update:  It appears that all configuration files include both channel pins (2 and 3) of the Pmod AD1. This meand that the second instance of Pmod will not work.

The driver seems to be the key. A comment in it says: "Only uses ADC2 use pin P3".

Hope to hear from the author of this driver (JonP) about possibility to include the second channel.

Also It appears that another version of the Pmod driver was created by Analog Devices three years ago for use with the FPGAs. I did not try it and wonder if anyone can comment on it.

[jpeyron]

Hi Notarobot,

Hamsters code is a great HDL solution for using the PmodDA1. In regards to the PmodAD1 IP, I have confirmed that we have added your request to update the PmodDA1 IP to support the two channels to our list of IP development/upgrade. Unfortunately, I would not be able to give you an ETA for this to be completed. Here and here are links to tutorials for making a custom IP.  In regards to the AXI one way to handle it is the axi_quad_spi in dual mode connected to the pmod_bridge using the product guide for setup as described above. Another way is writing your own custom spi controller that handles the non-standard spi communication. You could use the AXI GPIO controller the facilitate the communication between the spi controller and the AXI bus. The GPIO method will be less efficient in terms of resource usage than creating an IP core to do the same thing, but if you want to get  a project running quickly, might give it a shot. You will need to use AXI to communicate, and this is why you will need to use a GPIO controller.

cheer,

Jon 

[jpeyron]

Hi Notarbot,

I have passed on your request to upgrade the IP to use both channels. Which typically relates to us adding your request to our list of IP development/upgrade but I would not be able to give you an eta. I looked at the main file for the Analog Devices IP here and it does both channels so this might be your best option for both channels.

[Notarobot]

5 minutes ago, jpeyron said:

Hi Notarbot,

I have passed on your request to upgrade the IP to use both channels. Which typically relates to us adding your request to our list of IP development/upgrade but I would not be able to give you an eta. I looked at the main file for the Analog Devices IP here and it does both channels so this might be your best option for both channels.

I appreciate your response very much. Under these circumstances I will try try the Analod Devices driver while hoping that Digilent will upgrade the IP sooner than later.

In order to proceed I would like to ask you to provide me with the descriptions (purposes) of interface wires in  PmodAD1.v . These names are similar to the ones used by Analog Devices developers. This will help to cut time of my time studying datasheets and user guides. Any extra comments are greatly appreciated. Hardware drivers development is not my area of expertise.

Thank you!

 

[jpeyron]

Hi Notarbot,

I talked with the engineer that set up our communication part of our IP cores and his initial suggestion would be to try and use the  axi_quad_spi in dual mode connected to the pmod_bridge as shown below. You will want to right click on the axi_quad_spi and click on IP documentation and select view product guide to research futher on the dual mode and what it entails. I also briefly documented what the pins do in the .v file although altering this file will not help you get both channels working. 

cheers,

Jon

PmodAD1.v

[Notarobot]

Jon,

I will follow your advice. I was not going to touch .v file just wanted to know the designations. It seems to me that Verilog code is identical in both Digilent and Analod devices drivers.

Athough I am not 100% sure but in the Analog devices code the channel data are stacked in 32 bits, the first 16 bits is channel 1 and upper 16 bit - channel 2, or in reverse.

Assuming that the Verilog part of the code should be responsible for packaging the data, would it be that the second channel is already acquired and just C++ piece should be rewritten.

Anyway, thank you once more for your kind response and assistance.

Best regards!

[jpeyron]

Hi Notarobot,

The  axi_ad7476.v and axi_ad7476_dev_if.v of Analog Devices IP are different than our axi_quad_spi/ Pmod_bridge and is written to handle the non-traditional spi communications.  The hardware design that Analog Devices made is different than the Hardware design we used. They handle the 2 miso's where as we only handle the one master input pin.  

cheers,

Jon

 

[Notarobot]

Hi Jon,

Thank you for this update.

I need to compare both versions once more. At the first glance both designs are for the same Pmod AD1 hardware which has only one CS (MISO) pin. May be AD uses some different version. BTW, clk pin is also common. This means that ADC conversion is taking place on both channels simultaneously.

Also I have found another version of VHDL code dealing with Pmod AD1 with two channels here   I used to work with VHDL and feel more comfortable with it. I intend to test the code in simulation. The main issue for me is how to glue it to AXI_Lite. I assume that I need to create new custom IP block but this is new to me and I expect some learning time.

I would appreciate if you review the code in the link and share your recommendations.

Regards!

[Notarobot]

27 minutes ago, Notarobot said:

Just found these

 The same issue was discussed in the past.   

 

[Notarobot]

Jon,

Thank you, I am glad to hear that Pmod will soon reach this capability. 

BTW, I've found an HDL project called "Active Power Meter" completed by Digilent in 2005 and utilizing Pmod AD1. It is very well done.

Regarding to Pmod AD1 it appears to me that approach using AXI-SPI might lead to very significant complexity when more than one module is utilized. Not only a block diagram but also a C code become quite complicated. It might be a reason why only 1-channel solution was completed in the past. Another concern is that the time of execution would be diffuclt to predict because PS will be a master for all transations and because of complexity of the structure.

An alternative approach might be using HDL implementation for each module (2-channels) and shared BRAM for making data available to the processor. I am thinking to generate interrupt after writing a block of data for the processor to pick up the data. In this case the code on PS side would be just reading BRAM and data processing. HDL code is more transparant and latency is also should be easier to estimate. There are many details of implementation which are not clear to me but it seems to me that it would be possible to operate all modules at maximum speed.

What do you think about this solution? Does it make sense?