First : I'm a new in FPGA development For my experiments, I designed an IP module (in Verilog), which takes 3 inputs (clk, rst, walk[7:0]) and drives in funny way leds. Decided, that it's too much for this to use AXI memory mapped interface and used for control signal only 8-bit vector. My question is : can I use AXI GPIO with 8 bits output and connect only it's output vector to my IP's "walk" ? As I tried, the default value from GPIO works, but couldn't drive this value from the SDK at the address of the AXI GPIO ? Or may be some more clean way ?
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HI !
First : I'm a new in FPGA development For my experiments, I designed an IP module (in Verilog), which takes 3 inputs (clk, rst, walk[7:0]) and drives in funny way leds. Decided, that it's too much for this to use AXI memory mapped interface and used for control signal only 8-bit vector. My question is : can I use AXI GPIO with 8 bits output and connect only it's output vector to my IP's "walk" ? As I tried, the default value from GPIO works, but couldn't drive this value from the SDK at the address of the AXI GPIO ? Or may be some more clean way ?
Sorry, forgot : I test the design on Zybo....
Thank you in advance !
design_1.pdf
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