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Found 6 results

  1. Hi. I try to use four gpio on microblaze mcs. Two for imput and two por output. I can only read one input/output port. This is the verilog code. module TopMod( input sys_clk, input reset, input [7:0] sw, output [7:0] leds, input [7:0] sw1, output [7:0] leds1 ); microblaze_mcs_0 mcs_0 ( .Clk(sys_clk), .Reset(reset), .GPIO1_tri_i(sw), .GPIO1_tri_o(leds), .GPIO2_tri_i(sw1), .GPIO2_tri_o(leds1) ); endmodule and this is the sdk/ lenguaje c code #include <stdio.h> #include "platform.h" #include "xil_printf.h" #include "xparameters.h" #include "xiomodule.h" int main() { init_platform(); u32 data1; u32 data2; XIOModule gpi; XIOModule gpo; XIOModule gpi_1; XIOModule gpo_1; data1 = XIOModule_Initialize(&gpi, XPAR_IOMODULE_0_DEVICE_ID); data1 = XIOModule_Start(&gpi); data1 = XIOModule_Initialize(&gpo, XPAR_IOMODULE_0_DEVICE_ID); data1 = XIOModule_Start(&gpo); data2 = XIOModule_Initialize(&gpi_1, XPAR_IOMODULE_0_DEVICE_ID); data2 = XIOModule_Start(&gpi_1); data2 = XIOModule_Initialize(&gpo_1, XPAR_IOMODULE_0_DEVICE_ID); data2 = XIOModule_Start(&gpo_1); while (1) { data1 = XIOModule_DiscreteRead(&gpi, 1); // read switches (channel 1) XIOModule_DiscreteWrite(&gpo, 1, data1); // turn on LEDs (channel 1) data2 = XIOModule_DiscreteRead(&gpi_1, 1); // read switches (channel 2) XIOModule_DiscreteWrite(&gpo_1, 1, data2); // turn on LEDs (channel 2) } cleanup_platform(); return 0; } Can say to me whats is the problem? Thanks FF
  2. Hi, On my Arty A7 board i have the hello world running with Microblaze and UART. I added from the board tab the 4 buttons then i added the 4 LEDs. I'm using 2020.1, and by default it combined the AXI GPIO so there is a dual channel GPIO where both the leds and the buttons are connected. My problem is, that in Vitis the generated IO example code uses the same port, and only the buttons work... the device gets configured as such in the code: #define GPIO_OUTPUT_DEVICE_ID XPAR_GPIO_0_DEVICE_ID #define GPIO_INPUT_DEVICE_ID XPAR_GPIO_0_DEVICE_ID In xparameters.h i found this: /* Definitions for driver GPIO */ #define XPAR_XGPIO_NUM_INSTANCES 1 /* Definitions for peripheral AXI_GPIO_0 */ #define XPAR_AXI_GPIO_0_BASEADDR 0x40000000 #define XPAR_AXI_GPIO_0_HIGHADDR 0x4000FFFF #define XPAR_AXI_GPIO_0_DEVICE_ID 0 #define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0 #define XPAR_AXI_GPIO_0_IS_DUAL 1 /* Canonical definitions for peripheral AXI_GPIO_0 */ #define XPAR_GPIO_0_BASEADDR 0x40000000 #define XPAR_GPIO_0_HIGHADDR 0x4000FFFF #define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID #define XPAR_GPIO_0_INTERRUPT_PRESENT 0 #define XPAR_GPIO_0_IS_DUAL 1 The wizard creates two functions: GpioOutputExample( GPIO_OUTPUT_DEVICE_ID, GPIO_BITWIDTH); GpioInputExample(XPAR_AXI_GPIO_0_DEVICE_ID, &DataRead); input example works (buttons), but output does not (leds) Any help is appreciated! Csaba
  3. I followed this forum and changed the constraint files of the Zybo Z720 in Vivado and successfully generate bitstream and the xsa file to import into Vitis. https://forum.digilentinc.com/topic/8943-pmod-as-input-and-output-gpio/ #Pmod Header JE set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je_pin1_io }]; set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je_pin2_io }]; set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je_pin3_io }]; set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je_pin4_io }]; set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je_pin7_io }]; set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je_pin8_io }]; set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je_pin9_io }]; set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je_pin10_io }]; I am able to control the GPIO pins of port JF on the Zybo Z720 using the following code, how do I edit this so that I am able to turn on/off LEDs using the Pmod port JE instead. #include "xil_cache.h" #include "xparameters.h" #include "stdio.h" #include "xparameters.h" #include "xuartps.h" #include "xtime_l.h" #include "xgpiops.h" #include "sleep.h" #include "xil_io.h" #include "xil_types.h" #include "xil_printf.h" #include "sleep.h" #include "stdlib.h" #include "string.h" #define HOST_UART_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID #define HostUart XUartPs #define HostUart_Config XUartPs_Config #define HostUart_CfgInitialize XUartPs_CfgInitialize #define HostUart_LookupConfig XUartPs_LookupConfig #define HostUart_Recv XUartPs_Recv #define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->BaseAddress) #define PMODESP32_UART_BASEADDR XPAR_PMODESP32_0_AXI_LITE_UART_BASEADDR #define PMODESP32_GPIO_BASEADDR XPAR_PMODESP32_0_AXI_LITE_GPIO_BASEADDR #define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) #define TIMER_FREQ_HZ 100000000 #define MAX_WIDTH 320 #define MAX_HEIGHT 240 #define MAX_BUTTON 16 #ifdef __MICROBLAZE__ #define HOST_UART_DEVICE_ID XPAR_AXI_UARTLITE_0_BASEADDR #define HostUart XUartLite #define HostUart_Config XUartLite_Config #define HostUart_CfgInitialize XUartLite_CfgInitialize #define HostUart_LookupConfig XUartLite_LookupConfig #define HostUart_Recv XUartLite_Recv #define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->RegBaseAddr) #include "xuartlite.h" #include "xil_cache.h" #else #define HOST_UART_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID #define HostUart XUartPs #define HostUart_Config XUartPs_Config #define HostUart_CfgInitialize XUartPs_CfgInitialize #define HostUart_LookupConfig XUartPs_LookupConfig #define HostUart_Recv XUartPs_Recv #define HostUartConfig_GetBaseAddr(CfgPtr) (CfgPtr->BaseAddress) #include "xuartps.h" #endif #define PMODESP32_UART_BASEADDR XPAR_PMODESP32_0_AXI_LITE_UART_BASEADDR #define PMODESP32_GPIO_BASEADDR XPAR_PMODESP32_0_AXI_LITE_GPIO_BASEADDR #define BLOCK_SIZE 40 void startup(); XGpioPs_Config *ConfigPtr; XGpioPs output; int main() { startup(); while(1) { XGpioPs_WritePin(&output, 13, 1); //led on (pin 1,2,3,4) XGpioPs_WritePin(&output, 10, 1); XGpioPs_WritePin(&output, 11, 1); XGpioPs_WritePin(&output, 12, 1); } void startup(){ //initialize pins for JF ConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID); XGpioPs_CfgInitialize(&output, ConfigPtr, ConfigPtr->BaseAddr); XGpioPs_SetDirectionPin(&output, 13, 1); XGpioPs_SetOutputEnablePin(&output, 13,1); //pin1 JF1 XGpioPs_SetDirectionPin(&output, 10, 1); XGpioPs_SetOutputEnablePin(&output, 10,1); //pin2 JF2 XGpioPs_SetDirectionPin(&output, 11, 1); XGpioPs_SetOutputEnablePin(&output, 11,1); //pin3 JF3 XGpioPs_SetDirectionPin(&output, 12, 1); XGpioPs_SetOutputEnablePin(&output, 12,1); //pin4 JF4 }
  4. I wrote a simple vhdl design to test the gpio. Background story is that Im working on a more complex design which I rewrote two times until I come to the point that my electrical setup (which is quite simple) could be the problem. Stupid me! EDIT: I use the Arty board file and the xdc file provided by Digilent! Code of the simple test gpio design: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity io_test is generic( d_width : integer := 16; --width of each data word size : integer := 64; --number of data words the memory can store a_width : integer := 6 -- width of the adress bus ); port ( i_clk : in std_logic ; btn : in std_logic; led : out std_logic; led_2 : out std_logic; test_io : out std_logic_vector ((d_width + a_width + 1) downto 0) ); end io_test; architecture Behavioral of io_test is signal clk_counter : integer := 0; signal clk_1hz : std_logic := '0'; signal test_io_buf : std_logic_vector((d_width + a_width + 1) downto 0) := "000000000000000000000001"; signal insr : std_logic_vector(2 downto 0); signal led_buf : std_logic := '0'; begin btn_async : process(i_clk) begin if(rising_edge(i_clk)) then insr <= insr(1 downto 0) & btn; end if; end process; io_test : process (i_clk) begin if(rising_edge(i_clk) and i_clk ='1') then if (insr(2 downto 1) = "01") then test_io_buf <= test_io_buf(d_width + a_width downto 0) & '0'; led_buf <= not led_buf; end if; end if; end process; test_io <= test_io_buf; led <= btn; led_2 <= led_buf; end Behavioral; If I simulate the file with: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; entity test_of_ram is end test_of_ram; architecture Behavioral of test_of_ram is component io_test port( i_clk : in std_logic ; btn : in std_logic; test_io : out std_logic_vector ((16 + 6 + 1) downto 0); led : out std_logic ); end component; ------------------------------------------------------------------------------ -- Signals and Types ------------------------------------------------------------------------------ constant OFFSET : integer := 15; signal btn, clk : std_logic := '1'; signal led : std_logic; signal test_io : std_logic_vector ((16 + 6 + 1) downto 0); begin dev_to_test: io_test port map( btn => btn, test_io => test_io, i_clk => clk, led => led ); ------------------------------------------------------------------------------ -- Clock Stimulus ------------------------------------------------------------------------------ clk_stim : process begin wait for 5 ns; clk <= not clk; end process ; -- clk_stim ------------------------------------------------------------------------------ -- IO Stimulus ------------------------------------------------------------------------------ io : process variable cnt: integer := 0; begin for I in 1 to 16 loop wait for 100ns; btn <= not btn; end loop; end process ; -- read_write_stim end Behavioral; I get the following result: Which is exactly what I want. But led_2 never lights up and only gpio0 stays on 3.3V (measured with multimeter) xdc file: ## LEDs set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports led] set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports led_2 ]; #IO_25_35 Sch=led[5] #set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6] #set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7] ## Buttons set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn }]; #IO_L6N_T0_VREF_16 Sch=btn[0] #set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1] #set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2] #set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3] ## Clock signal set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports i_clk] create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports i_clk] #set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] ## ChipKit Outer Digital Header set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {test_io[0]}] set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {test_io[1]}] set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {test_io[2]}] set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {test_io[3]}] set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {test_io[4]}] set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {test_io[5]}] set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {test_io[6]}] set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { test_io[7] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7] set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {test_io[8]}] set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {test_io[9]}] set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {test_io[10]}] set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {test_io[11]}] set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {test_io[12]}] set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {test_io[13]}] ## ChipKit Inner Digital Header set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {test_io[14]}] set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {test_io[15]}] set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {test_io[16]}] #set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ram_addr[1] }]; #IO_25_14 Sch=ck_io[29] set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports {test_io[17]}] set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {test_io[18]}] set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {test_io[19]}] set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {test_io[20]}] #set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { test_io[21] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34] #set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { test_io[22] }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35] set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports test_io[21]] #set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {test_io[7]}] set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {test_io[22]}] set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {test_io[23]}] #set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40] #set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
  5. Hello everyone. I am learning UART communication with Nexys video board. Using only IP integrator, I succeed to 'turn on the LEDs with SWs' and now, I tried to use custom counter module by Verilog. module clock_divider( input clk, input [4:0]key, output reg [7:0]led ); //we will need one register to keep the clock count number; reg [22:0] count; always @(posedge clk) // judge the clk rise edge; if (key) begin // if the key has been pressed, if(count==0) begin // then count value flip over to zero, then make led on or off led <= ~led; // in the always loop, it needs to use registers end count <= count +1; // add the count value until it flips over to zero end else begin // if there is no key to be pressed, init the led to off state; led <=0; count <=1; end endmodule and I included this module in IP design. and the errors were like below. before this errors, I connected slight different module~IP wiring , and the result was ' synthesis & implement succeed, Bitstream failed' I'm looking for some information on google, but hard to find out my problem. can you give me some hints or solution? Thank you for your kind answers, ...
  6. I am learning how to operate an FPGA, and I have to input a signal (which in itself is the output of a discriminator), and analyze it through a Basys3 FPGA. Looking at the available ports on the board, I'm guessing that it could be done using the Pmod ports, but even after hours of googling and going through the manuals, I failed to know which data ports to use, and how to read the signal after I've input it through the board. I've got references to some boards, in which GPIO ports are explicitly labelled, but I don't see any such labeling on the Basys3. So, it'd be really helpful if someone can provide me with any insight regarding this. Any other references or links would also be greatly appreciated. I've already gone through the basic tutorials (like lighting the led using the switch. I just want to know how to use the input ports, and analyze my signal. Thank You
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