Design with AXI TG ip core

[vvk]

Hi,
  I am working with zed board.I am new to  hardware design with ip core. I want to develop an hw design using AXI TG ip core in which I want to transfer the random data which comes from the ip core and receive the same data in buffer. Can any one please help me out how to create a block design for it by using available ip cores in Vivado 2015.2.
 
    please provide any referrence design too. Thanks in advance

[jpeyron]

Hi vvk,

Unfortunately we do not have any demos or tutorials that utilize the axi traffic generator that i am aware of. Here Is a link to some github examples using the AXI traffic generator. Here is a pdf that has some information about the AXI TG. Here is a thread you posted that talks about the example provided with the IP. Here is the user guide for the AXI traffic generator.

cheers,

Jon