I have a hardware design using the Zmod ADC that runs but the axi streams are "Inactive". I tried changing the clock source from the Zynq processor, as some previous error suggested an issue but the design seems to work as I get tdata out of the ADC and am able to use DSP on the data but the AXI stream isn't working.
Any basic Ideas? I'm using the old 1410 IP, pre scope, no level triggers, just enable acquisition with a digital. Attached are the block design and the ILA scope screen capture.
I've searched some Xilinx forums but nothing jumps out, something about "instantiating" that I don't understand. Perhaps somebody here can help.
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Xband
Greetings,
I have a hardware design using the Zmod ADC that runs but the axi streams are "Inactive". I tried changing the clock source from the Zynq processor, as some previous error suggested an issue but the design seems to work as I get tdata out of the ADC and am able to use DSP on the data but the AXI stream isn't working.
Any basic Ideas? I'm using the old 1410 IP, pre scope, no level triggers, just enable acquisition with a digital. Attached are the block design and the ILA scope screen capture.
I've searched some Xilinx forums but nothing jumps out, something about "instantiating" that I don't understand. Perhaps somebody here can help.
Thanks,
design_1.pdf
Edited by Xbandupdate
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