Inactive Axi Stream in hardware Zmod 1410, EclypseZ7

[Xband]

Greetings, 

I have a hardware design using the Zmod ADC that runs but the axi streams are "Inactive".  I tried changing the clock source from the Zynq processor, as some previous error suggested an issue but the design seems to work as I get tdata out of the ADC and am able to use DSP on the data but the AXI stream isn't working. 

Any basic Ideas?  I'm using the old 1410 IP, pre scope, no level triggers, just enable acquisition with a digital.  Attached are the block design and the ILA scope screen capture. 

I've searched some Xilinx forums but nothing jumps out, something about "instantiating" that I don't understand.  Perhaps somebody here can help. 

Thanks, 

 

 

design_1.pdf

Edited May 24 by Xband
update

[artvvb]

Hey XBand,

How are you starting the ILA, using Run Trigger Immediate? Setting up a trigger should let you narrow in on only when interesting events are happening, by doing something like triggering on a read address channel tvalid signal being high at the same time as the corresponding tready signal. Pairing ILAs with the Vitis debugger can also be helpful, so that you can manually step through code and precisely control what state the hardware and software are in when you run the ILA. If a trigger set up to trigger on valid and ready for some channel never fires, it means that that stream isn't being used at all.

The screenshot below shows a trigger setup. It's not a meaningful one in this case, just a project I happened to have open, but hopefully helps for seeing the UI. In the trigger setup pane, the plus button adds signals to the trigger. The "And gate" icon shows that everything in the list below must be true for a trigger to occur. In this case, a trigger occurs when the pLockLostRst signal is high, and the dbg_pBitslip bus matches "3" (3'b011). The Settings pane gives a little bit more info - the trigger position in window field specifies where in the chart the trigger condition will be displayed; changing it lets you see more data in front of or behind the trigger condition. The window data depth shows how many clock cycles the ILA is capturing.

4 hours ago, Xband said:

I tried changing the clock source from the Zynq processor, as some previous error suggested an issue but the design seems to work as I get tdata out of the ADC and am able to use DSP on the data but the AXI stream isn't working. 

The ILA should always be driven by the clock associated with the AXI stream interface, and I'd expect to see build errors when that isn't the case.

Thanks,

Arthur

[Xband]

@artvvb, 

I'm triggering omn the data coming from the ADC, perhaps the AXI doesn't have time to get started?

 

[artvvb]

I think "X" for a value in a bus means "don't care", so it will trigger on anything, meaning that run trigger and run trigger immediate are effectively doing the same thing - which is a long way of saying that yes, the channel might not have time to start before data is captured from it. Try something like this, valid and ready are only both high when data is moving:

[Xband]

I'm also running different Vitis Software dShow Replyebugger projects, sometimes to get the ILA to trigger.