Xband

Hi, I have what seems to be a working hardware design with the Zmod 1410 scope module (see below). My thought then was to modify the DDR example code removing all references to "triggering" (I don't care about that at this point) and recycle the multi S2MM_cyclic_transfer_test example. I created a new "helloworld" application in Vitis, copied the main.c from the above application and rebuilt the project. Then added what seemed to be relevant libraries in the main.c file. I did this 2 times and am having the same problem with the UserRegister path, I've built and cleaned the project, the cleaned version looks like it should run but then cannot find a valid platform when I try to launch from the Debug hardware option. Seems to be the same path issue for both versions, I was worried the "datatrans_" directory path was causing some problem so built the new "axidata" version. The scope below shows a 1MHz sine wave with 100MHz ADC sample from the Zmod and the lower sawtooth is a DSP accumulator. These seem ok before the AXI stuff happens is why I claim the hardware design is ok. Any ideas on what could be the problem? Thanks, Error: Error while launching program: The platform 'C:/GitHub/WN_Zmod/Vitis_notrig/design_1_wrapper_1/export/design_1_wrapper_1/design_1_wrapper_1.xpfm' used by the system project 'axidata_system' is not valid. The platform 'C:/GitHub/WN_Zmod/Vitis_notrig/design_1_wrapper_1/export/design_1_wrapper_1/design_1_wrapper_1.xpfm' used by the system project 'axidata_system' is not valid. Description Resource Path Location Type Invalid project path: Include path not found (C:\..\GitHub\WN_Zmod\Vitis_notrig\datatrans_\Debug\_sdk\bsp\ps7_cortexa9_0\include). datatrans_ pathentry Path Entry Problem Description Resource Path Location Type Invalid project path: Include path not found (C:\..\GitHub\WN_Zmod\Vitis_notrig\design_1_wrapper_1\export\design_1_wrapper_1\sw\design_1_wrapper_1\standalone_ps7_cortexa9_0\bspinclude\include). axidata pathentry Path Entry Problem

Are these addresses constant for the Eclypse Z7 platform or do you need to look at this file each time when wanting to get data? I was wondering how these came about, does building an application in Vitis automatically assign the values or properly route existing hardware values? or other magic? Thanks,

@artvvb, Moving that definition fixed it on my side too, thanks for a small win here and great instructions getting through the process. I found this quite valuable as a training intro to the ILA process. Cant say I would have successfully debugged and found the problem but its a good step in the process! Glossed over the bit about triggering the acquisition twice and seeing the difference in the buffer. My success was getting all of your steps to line up and work. Spent 2 days messing around after trying to address a buffer overflow diagnosis from the AMD help site, finally restored the settings and things worked after rebooting the machine. This platform seems to have an infinite number of issues to deal with. Thanks again for the help!

@artvvb, thanks for putting this together. I'll need some time to absorb all that is going on, its a great tutorial.

@artvvb, Thanks for noticing, exactly what in this ILA scope could lead you to this diagnosis?

@artvvb Not sure if its successful or not, looks like it read 64 bits, 0-63, though the added code says test failed. Not sure how to interpret the result. I was going to move this topic to a new thread but not sure of a smooth process for doing so. thanks for insight.

@artvvb, When I run this the data never flows into the while loop in the software, my serial terminal output is a few "test done" printf statements. When the ILA is launched it is "waiting for trigger" 0 of 1024 samples. Is there an obvious problem? Thanks,

@artvvb, can you elaborate a bit on the control_0 part of this design? Are these just 2 GPIO blocks? Its impossible to tell what they are connected to, my options for the Z7 are the button or leds. It seems like the data is streaming from this gpio. Otherwise this seems like a nice instructional piece of code, but for this exclusion. Sorry it may be obvious to some. Thanks,

@rarow, I did a similar thing with pulsed LED with triggering a camera. I couldn't see the LED since the pulse was so short it didn't make enough light for me to see with my eyes. Though I finally timed the camera so I could see the led flashing, so you might need better eyes! :)

Could also be termination of the signal contributing to this. Typically there can be a factor of 2 if you’re reading a 50ohm termination at high impedance 1Mohm. I cannot recast what the zmod sma termination is, but I know it’s listed numerous places in the documentation.

@artvvb, continuing to beat this dead horse. Attached is a pdf of the hardware design that seems to compile and can generate a bitstream, though with some errors. The DDR software will run but since the multi streaming code is written for a 32bit buffer I cant extract it. I went into the HW code and made the original AXI stream 64bits depth and tried to change appropriate buffer indexing in the s2mm_cyclic_transfer code but cannot get to the data. I"m not sure this was successful. I've changed the u32 for the Bufferlength to u64 and tried to propagate these changes to indexing through to multi streaming main code. Could you give a rough overview on which values should change to u64 (in the s2mm_cyclic_transfer main) or perhaps just a link to some code that would spit the actual hardware buffer out so I can confirm it has changed to 64bit depth. I seen to recall you being against changing this depth to 64, which is entirely reasonable given the complexity that the stream depends on, I tried to preserve the 32bit axi stream data through all the original hw in the base fpga design and then combine the stream just befor the DMA transfer coming out of the ZmodScope Port A. I think the basic concept of pulling out the data, using the DSP accumulator and then combining back into the AXI stream should work, though I could be really screwed up with the timing even if it compiles. I'm interested in using the simulation to try and ring out the timing but this DDR project is pretty deep and I'm not sure how to implement that, though I see you have the ILA ip scattered throughout for this purpose. Have a good weekend, sorry I always post these on Friday but I'll typically work through the week trying to get something going and then succumb to the frustration later in the week. Thanks for any help. ZmodScope_PortA_2_9_2024.pdf

Deleted post.

@artvb Hi, I was able to get my modifications to the DDR project to compile and run with the baseline streaming sw project, though the project added DSP integration of the ADC values are not integrating. I tried to replace the ADC output in the stream with the integration values from each channel though I'm still getting the baseline values coming through. My current guess is that there is an issue with the triggering and/or the writing into the AXI stream isn't working properly. To try and diagnose and understand more wanted to run the simulation and ring out the triggering and clocks to help with understanding, but am getting a silly error that I've found others having in the AMD forums, "default_nettype is none" issues with a couple of clock signals. Another problem is that the Vitis project seems to be locked and will not allow me so save my changes, thus every time I launch the project from scratch I need to go back and redo. I know this is a bit vague, but I could use a bit of direction if you have any suggestions. Thanks!

@artvvb, Thanks for the help, I just cheated and copied the bit file it was complaining about into the directory. It actually ran, while that is good I'll follow your directions and try to clean it all up. Glad that my setup isn't necessarily bad with the Win10, though it seems I"m able to find every way to mess things up. Thanks again.

Now perhaps I've had every version of this problem, now the log says its loading the correct bit file but the error pops up with an old one. Hi, I have a modified streaming DDR program that I want to test changes I've made to the fpga from a working version of the DDR streaming example. I have loaded and confirmed software Vitis project is working, calibration read and S2mm_cyclic_transfer work. The "easiest" solution would be to read the xsa export into the Vitis application after confirming the working software, at least this seems straightforward. Though I have struggled with these applications getting all of the source files to read properly and have had a night mare resetting the BSP what seems like hundreds of times to finally get the Vitis project to work consistently. Not sure I want to deal again with fallout of destroying a working project through the process. Any advice on the best way to approach this? Running the projects on a Win10 machine Vivado 2023.1. Is this a particularly buggy setup in general? Also I cannot save, or Save As from the Vitis File menu, it is greyed out so none of the changes can be saved at the project level. Thanks,

Seemed to have everything compiled in the hardware, went to Vitis in and rebuilt the project seemed ok, had issues getting anything to respond after programming the device over and over. Switched to another board which I have and then had this strange error which probably comes from the "calibration" routine. Had previously run the demo which is why there are "button x pressed!" in the serial display. "Unsupported Zmod" was after reprogramming the fpga and then loading the software from Vitis. Try more later.

@artvvb, updated the ip and things seem better, creating a new HDL wrapper and will try synthesis. Got through synthesis and implementation. A timing failure. Bitstream generated fine. Will try to load onto the hardware when I get a chance. Upgrading the IP seemed to resolve the issue. I wasn't sure if it should be done, let sleeping dogs lie was my approach until spiraling into the doghouse. Thanks for the support.

@zygot yeah I had the main project working quickly also, its the modifications that cause problems and the accompanying gaps in the workflow in Vivado that come along. I search Xilinx forums each time before reposting here and find people encountering the exact problems I am having years ago and there are not clear solutions to the same annoyance I'm having. Part of my problem could be I'm using 2023.1 and the original project is in 20xx.x, I don't know. At some point I might download the same version and go through it. The current stumbling block is that Vivado changed the directory for ip from the baseline to a "temporary" and seemed to forget it does this for some reason. So I as a novice need to figure out what trick I can pull to make it ok. Maybe rebuilding the project in an earlier version is the best solution at this point, I don't know.

Thanks, that's helpful. I've been at this sporadically while taking care of a family member who has been in and out of the hospital. Again I don't see it as a problem with the hardware, Vivado is a mess and non intuitive, I'm using the proper platform for my application . I"ve been cordial with your drop in remarks, I suggest you unfollow the conversation if you don't have anything to contribute.

This is getting worse, now it doesn't see the "design_1" wrapper file.... saw something about if you move between simulation and design it places things in an "imports" folder that can cause issues, though I don't see a solution for this issue. C:/Users/LENOVO/Documents/GitHub/hw/hw.srcs/sources_1/imports/hdl/design_1_wrapper.v

report_ip_status, Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 | Date : Wed Dec 27 11:54:12 2023 | Host : DESKTOP-A1N1QKI running 64-bit major release (build 9200) | Command : report_ip_status --------------------------------------------------------------------------------------------------------------------------------------------- IP Status Summary 1. Project IP Status -------------------- Your project uses 142 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions. More information on the Xilinx versioning policy is available at www.xilinx.com. Project IP Instances +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part | | | | | Log | | Version | | License | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | c_accum_0 | Up-to-date | No changes required | *(1) | Accumulator | 12.0 | 12.0 (Rev. 15) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 15) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_AxiStreamSinkMonitor_0_0 | Up-to-date | No changes required | Change | AxiStreamSinkMonit | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 2) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_AxiStreamSourceMonit_0_0 | Up-to-date | No changes required | Change | AxiStreamSourceMon | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 2) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_ManualTrigger_0_0 | Up-to-date | No changes required | Change | ManualTrigger | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 2) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_TriggerControl_0_0 | Up-to-date | No changes required | Change | TriggerControl | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 2) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_UserRegisters_0_0 | Up-to-date | No changes required | Change | UserRegisters | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 2) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_ZmodAWGController_0_0 | Up-to-date | No changes required | Change | ZmodAWGController_ | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 2) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_ZmodAwgAxiConfigurat_0_0 | Up-to-date | No changes required | Change | ZmodAwgAxiConfigur | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 2) | | | | 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design_1_axi_lite_rst_1 | Up-to-date | No changes required | *(6) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_axi_lite_rst_2 | Up-to-date | No changes required | *(7) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_axi_reset_0 | Up-to-date | No changes required | *(8) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_axi_rst1_0 | Up-to-date | No changes required | *(9) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_axi_rst_0 | Up-to-date | No changes required | *(10) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | 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+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_axis_clock_converter_0_0 | IP revision change | Upgrade IP | *(13) | AXI4-Stream Clock | 1.1 | 1.1 (Rev. 29) | Included | xc7z020clg484-1 | | | | | | Converter | (Rev. | | | | | | | | | | 25) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_axis_clock_converter_0_1 | IP revision change | Upgrade IP | *(14) | AXI4-Stream Clock | 1.1 | 1.1 (Rev. 29) | Included | xc7z020clg484-1 | | | | | | Converter | (Rev. | | | | | | | | | | 25) | | | | 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+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_axis_mux_0_0 | Up-to-date | No changes required | Change | axis_mux_v1_0 | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 1) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_axis_register_slice_0_0 | IP revision change | Upgrade IP | *(17) | AXI4-Stream | 1.1 | 1.1 (Rev. 28) | Included | xc7z020clg484-1 | | | | | | Register Slice | (Rev. | | | | | | | | | | 24) | | | | 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+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_c_accum_1_0 | Up-to-date | No changes required | *(20) | Accumulator | 12.0 | 12.0 (Rev. 15) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 15) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_clk_wiz_0_0 | IP revision change | Upgrade IP | *(21) | Clocking Wizard | 6.0 | 6.0 (Rev. 12) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 8) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_clk_wiz_0_1 | IP revision change | Upgrade IP | *(22) | Clocking Wizard | 6.0 | 6.0 (Rev. 12) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 8) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_create_tlast_0_0 | Up-to-date | No changes required | Change | create_tlast_v1_0 | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 1) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_extend_pulse_0_0 | Up-to-date | No changes required | Change | extend_pulse_v1_0 | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 1) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_fclk1_rst1_0 | Up-to-date | No changes required | *(23) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | 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+-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_fclk2_rst_0 | Up-to-date | No changes required | *(26) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_ila_0_0 | IP revision change | Upgrade IP | *(27) | ILA (Integrated | 6.2 | 6.2 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Logic Analyzer) | (Rev. | | | | | | | | | | 11) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_inject_tlast_on_trig_0_0 | Up-to-date | No changes required | Change | inject_tlast_on_tr | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 1) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_level_trigger_0_0 | Up-to-date | No changes required | Change | level_trigger_v1_0 | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 1) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_mm2s_rst_0 | Up-to-date | No changes required | *(28) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_processing_system7_0_0 | Up-to-date | No changes required | *(29) | ZYNQ7 Processing | 5.5 | 5.5 (Rev. 6) | Included | xc7z020clg484-1 | | | | | | System | (Rev. | | | | | | | | | | 6) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_ps7_0_axi_periph_gp0_0 | IP revision change | Upgrade IP | *(30) | AXI Interconnect | 2.1 | 2.1 (Rev. 29) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 25) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_resolution_0 | Up-to-date | No changes required | *(31) | Slice | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 2) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_sg_rst1_0 | Up-to-date | No changes required | *(32) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_sg_rst2_0 | Up-to-date | No changes required | *(33) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_sg_rst3_0 | Up-to-date | No changes required | *(34) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_sg_rst4_0 | Up-to-date | No changes required | *(35) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_sg_rst_0 | Up-to-date | No changes required | *(36) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_smartconnect_0_0 | IP revision change. IP contains locked subcore | Upgrade IP | *(37) | AXI SmartConnect | 1.0 | 1.0 (Rev. 20) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 16) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_smartconnect_1_0 | IP revision change. IP contains locked subcore | Upgrade IP | *(38) | AXI SmartConnect | 1.0 | 1.0 (Rev. 20) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 16) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_smartconnect_2_0 | IP revision change. IP contains locked subcore | Upgrade IP | *(39) | AXI SmartConnect | 1.0 | 1.0 (Rev. 20) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 16) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_stream_rst_0 | Up-to-date | No changes required | *(40) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_stream_rst_1 | Up-to-date | No changes required | *(41) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_stream_rst_2 | Up-to-date | No changes required | *(42) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_stream_rst_3 | Up-to-date | No changes required | *(43) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_stream_rst_4 | Up-to-date | No changes required | *(44) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_system_ila_0_0 | IP revision change. IP contains locked subcore | Upgrade IP | *(45) | System ILA | 1.1 | 1.1 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 10) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_system_ila_1_0 | IP revision change. IP contains locked subcore | Upgrade IP | *(46) | System ILA | 1.1 | 1.1 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 10) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_test_stream_sink_0_0 | Up-to-date | No changes required | Change | test_stream_sink_v | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 1) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_traffic_generator_0_0 | Up-to-date | No changes required | Change | traffic_generator_ | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 1) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_xlconcat_0_0 | Up-to-date | No changes required | *(47) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_xlconcat_0_1 | Up-to-date | No changes required | *(48) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_xlconcat_1_0 | Up-to-date | No changes required | *(49) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_xlslice_0_0 | Up-to-date | No changes required | *(50) | Slice | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 2) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_xlslice_15_downto_0_1 | Up-to-date | No changes required | *(51) | Slice | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 2) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_xlslice_1_0 | Up-to-date | No changes required | *(52) | Slice | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 2) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | design_1_xlslice_31_downto_16_1 | Up-to-date | No changes required | *(53) | Slice | 1.0 | 1.0 (Rev. 2) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 2) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | ZmodADC_SynchonizationFIFO | IP revision change | Upgrade parent IP | *(54) | FIFO Generator | 13.2 | 13.2 (Rev. 8) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 5) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_365d_g_inst_0 | Incompatible IP data detected | Repackage parent IP | Change | Gigantic mux | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 1) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_365d_ila_lib_0 | IP revision change | Repackage parent IP | *(55) | ILA (Integrated | 6.2 | 6.2 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Logic Analyzer) | (Rev. | | | | | | | | | | 11) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_arsw_0 | Up-to-date | No changes required | *(56) | SmartConnect | 1.0 | 1.0 (Rev. 6) | Included | xc7z020clg484-1 | | | | | | Switchboard | (Rev. | | | | | | | | | | 6) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_awsw_0 | Up-to-date | No changes required | *(57) | SmartConnect | 1.0 | 1.0 (Rev. 6) | Included | xc7z020clg484-1 | | | | | | Switchboard | (Rev. | | | | | | | | | | 6) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_bsw_0 | Up-to-date | No changes required | *(58) | SmartConnect | 1.0 | 1.0 (Rev. 6) | Included | xc7z020clg484-1 | | | | | | Switchboard | (Rev. | | | | | | | | | | 6) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_m00arn_0 | IP revision change | Repackage parent IP | *(59) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_m00awn_0 | IP revision change | Repackage parent IP | *(60) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_m00bn_0 | IP revision change | Repackage parent IP | *(61) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_m00e_0 | IP revision change | Repackage parent IP | *(62) | SC EXIT | 1.0 | 1.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 11) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_m00rn_0 | IP revision change | Repackage parent IP | *(63) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_m00s2a_0 | IP revision change | Repackage parent IP | *(64) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7z020clg484-1 | | | | | | SC2AXI Bridge | (Rev. | | | | | | | | | | 7) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_m00wn_0 | IP revision change | Repackage parent IP | *(65) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_one_0 | Incompatible IP data detected | Repackage parent IP | *(66) | Constant | 1.1 | 1.1 (Rev. 7) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 7) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_psr_aclk_0 | Up-to-date | No changes required | *(67) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_rsw_0 | Up-to-date | No changes required | *(68) | SmartConnect | 1.0 | 1.0 (Rev. 6) | Included | xc7z020clg484-1 | | | | | | Switchboard | (Rev. | | | | | | | | | | 6) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_s00a2s_0 | IP revision change | Repackage parent IP | *(69) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7z020clg484-1 | | | | | | AXI2SC Bridge | (Rev. | | | | | | | | | | 7) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_s00mmu_0 | IP revision change | Repackage parent IP | *(70) | SC MMU | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 10) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_s00sic_0 | IP revision change | Repackage parent IP | *(71) | SC SI_CONVERTER | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 10) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_s00tr_0 | Up-to-date | No changes required | *(72) | SC | 1.0 | 1.0 (Rev. 9) | Included | xc7z020clg484-1 | | | | | | TRANSACTION_REGULA | (Rev. | | | | | | | | | | 9) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_s01a2s_0 | IP revision change | Repackage parent IP | *(73) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7z020clg484-1 | | | | | | AXI2SC Bridge | (Rev. | | | | | | | | | | 7) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_s01mmu_0 | IP revision change | Repackage parent IP | *(74) | SC MMU | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 10) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_s01sic_0 | IP revision change | Repackage parent IP | *(75) | SC SI_CONVERTER | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 10) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_s01tr_0 | Up-to-date | No changes required | *(76) | SC | 1.0 | 1.0 (Rev. 9) | Included | xc7z020clg484-1 | | | | | | TRANSACTION_REGULA | (Rev. | | | | | | | | | | 9) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_sarn_0 | IP revision change | Repackage parent IP | *(77) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_sarn_1 | IP revision change | Repackage parent IP | *(78) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_sawn_0 | IP revision change | Repackage parent IP | *(79) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_sawn_1 | IP revision change | Repackage parent IP | *(80) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_sbn_0 | IP revision change | Repackage parent IP | *(81) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_sbn_1 | IP revision change | Repackage parent IP | *(82) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_srn_0 | IP revision change | Repackage parent IP | *(83) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_srn_1 | IP revision change | Repackage parent IP | *(84) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_swn_0 | IP revision change | Repackage parent IP | *(85) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_swn_1 | IP revision change | Repackage parent IP | *(86) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_48ac_wsw_0 | Up-to-date | No changes required | *(87) | SmartConnect | 1.0 | 1.0 (Rev. 6) | Included | xc7z020clg484-1 | | | | | | Switchboard | (Rev. | | | | | | | | | | 6) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_880d_m00e_0 | IP revision change | Repackage parent IP | *(88) | SC EXIT | 1.0 | 1.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 11) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_880d_m00s2a_0 | IP revision change | Repackage parent IP | *(89) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7z020clg484-1 | | | | | | SC2AXI Bridge | (Rev. | | | | | | | | | | 7) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_880d_one_0 | Incompatible IP data detected | Repackage parent IP | *(90) | Constant | 1.1 | 1.1 (Rev. 7) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 7) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_880d_psr_aclk_0 | Up-to-date | No changes required | *(91) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_880d_s00a2s_0 | IP revision change | Repackage parent IP | *(92) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7z020clg484-1 | | | | | | AXI2SC Bridge | (Rev. | | | | | | | | | | 7) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_880d_s00mmu_0 | IP revision change | Repackage parent IP | *(93) | SC MMU | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 10) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_880d_s00sic_0 | IP revision change | Repackage parent IP | *(94) | SC SI_CONVERTER | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 10) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_880d_s00tr_0 | Up-to-date | No changes required | *(95) | SC | 1.0 | 1.0 (Rev. 9) | Included | xc7z020clg484-1 | | | | | | TRANSACTION_REGULA | (Rev. | | | | | | | | | | 9) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_880d_sarn_0 | IP revision change | Repackage parent IP | *(96) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_880d_srn_0 | IP revision change | Repackage parent IP | *(97) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_88fd_m00e_0 | IP revision change | Repackage parent IP | *(98) | SC EXIT | 1.0 | 1.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 11) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_88fd_m00s2a_0 | IP revision change | Repackage parent IP | *(99) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7z020clg484-1 | | | | | | SC2AXI Bridge | (Rev. | | | | | | | | | | 7) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_88fd_one_0 | Incompatible IP data detected | Repackage parent IP | *(100) | Constant | 1.1 | 1.1 (Rev. 7) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 7) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_88fd_psr_aclk_0 | Up-to-date | No changes required | *(101) | Processor System | 5.0 | 5.0 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Reset | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_88fd_s00a2s_0 | IP revision change | Repackage parent IP | *(102) | SmartConnect | 1.0 | 1.0 (Rev. 8) | Included | xc7z020clg484-1 | | | | | | AXI2SC Bridge | (Rev. | | | | | | | | | | 7) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_88fd_s00mmu_0 | IP revision change | Repackage parent IP | *(103) | SC MMU | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 10) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_88fd_s00sic_0 | IP revision change | Repackage parent IP | *(104) | SC SI_CONVERTER | 1.0 | 1.0 (Rev. 11) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 10) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_88fd_s00tr_0 | Up-to-date | No changes required | *(105) | SC | 1.0 | 1.0 (Rev. 9) | Included | xc7z020clg484-1 | | | | | | TRANSACTION_REGULA | (Rev. | | | | | | | | | | 9) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_88fd_sawn_0 | IP revision change | Repackage parent IP | *(106) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_88fd_sbn_0 | IP revision change | Repackage parent IP | *(107) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_88fd_swn_0 | IP revision change | Repackage parent IP | *(108) | SmartConnect Node | 1.0 | 1.0 (Rev. 14) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 13) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_g_inst_0 | Incompatible IP data detected | Repackage parent IP | Change | Gigantic mux | 1.0 | 1.0 (Rev. 1) | Included | xc7z020clg484-1 | | | | | Log not | | (Rev. | | | | | | | | available | | 1) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_ila_lib_0 | IP revision change | Repackage parent IP | *(109) | ILA (Integrated | 6.2 | 6.2 (Rev. 13) | Included | xc7z020clg484-1 | | | | | | Logic Analyzer) | (Rev. | | | | | | | | | | 11) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_0_ar_0 | Up-to-date | No changes required | *(110) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_0_aw_0 | Up-to-date | No changes required | *(111) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_0_b_0 | Up-to-date | No changes required | *(112) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_0_r_0 | Up-to-date | No changes required | *(113) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_0_w_0 | Up-to-date | No changes required | *(114) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_1_ar_0 | Up-to-date | No changes required | *(115) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_1_aw_0 | Up-to-date | No changes required | *(116) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_1_b_0 | Up-to-date | No changes required | *(117) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_1_r_0 | Up-to-date | No changes required | *(118) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_1_w_0 | Up-to-date | No changes required | *(119) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_2_ar_0 | Up-to-date | No changes required | *(120) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_2_aw_0 | Up-to-date | No changes required | *(121) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_2_b_0 | Up-to-date | No changes required | *(122) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_2_r_0 | Up-to-date | No changes required | *(123) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ | bd_f60c_slot_2_w_0 | Up-to-date | No changes required | *(124) | Concat | 2.1 | 2.1 (Rev. 4) | Included | xc7z020clg484-1 | | | | | | | (Rev. | | | | | | | | | | 4) | | | | +-----------------------------------+------------------------------------------------+-----------------------------------+-----------+--------------------+---------+----------------+------------+----------------------+ *(1) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/c_accum_v12_0/doc/c_accum_v12_0_changelog.txt *(2) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axi_dma_v7_1/doc/axi_dma_v7_1_changelog.txt *(3) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axi_dma_v7_1/doc/axi_dma_v7_1_changelog.txt *(4) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axi_fifo_mm_s_v4_3/doc/axi_fifo_mm_s_v4_3_changelog.txt *(5) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(6) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(7) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(8) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(9) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(10) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(11) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(12) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(13) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axis_clock_converter_v1_1/doc/axis_clock_converter_v1_1_changelog.txt *(14) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axis_clock_converter_v1_1/doc/axis_clock_converter_v1_1_changelog.txt *(15) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axis_clock_converter_v1_1/doc/axis_clock_converter_v1_1_changelog.txt *(16) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axis_clock_converter_v1_1/doc/axis_clock_converter_v1_1_changelog.txt *(17) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axis_register_slice_v1_1/doc/axis_register_slice_v1_1_changelog.txt *(18) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axis_register_slice_v1_1/doc/axis_register_slice_v1_1_changelog.txt *(19) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/c_accum_v12_0/doc/c_accum_v12_0_changelog.txt *(20) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/c_accum_v12_0/doc/c_accum_v12_0_changelog.txt *(21) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/clk_wiz_v6_0/doc/clk_wiz_v6_0_changelog.txt *(22) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/clk_wiz_v6_0/doc/clk_wiz_v6_0_changelog.txt *(23) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(24) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(25) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(26) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(27) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/ila_v6_2/doc/ila_v6_2_changelog.txt *(28) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(29) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/processing_system7_v5_5/doc/processing_system7_v5_5_changelog.txt *(30) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt *(31) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/xlslice_v1_0/doc/xlslice_v1_0_changelog.txt *(32) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(33) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(34) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(35) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(36) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(37) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/smartconnect_v1_0/doc/smartconnect_v1_0_changelog.txt *(38) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/smartconnect_v1_0/doc/smartconnect_v1_0_changelog.txt *(39) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/smartconnect_v1_0/doc/smartconnect_v1_0_changelog.txt *(40) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(41) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(42) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(43) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(44) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(45) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/system_ila_v1_1/doc/system_ila_v1_1_changelog.txt *(46) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/system_ila_v1_1/doc/system_ila_v1_1_changelog.txt *(47) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/xlconcat_v2_1/doc/xlconcat_v2_1_changelog.txt *(48) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/xlconcat_v2_1/doc/xlconcat_v2_1_changelog.txt *(49) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/xlconcat_v2_1/doc/xlconcat_v2_1_changelog.txt *(50) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/xlslice_v1_0/doc/xlslice_v1_0_changelog.txt *(51) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/xlslice_v1_0/doc/xlslice_v1_0_changelog.txt *(52) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/xlslice_v1_0/doc/xlslice_v1_0_changelog.txt *(53) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/xlslice_v1_0/doc/xlslice_v1_0_changelog.txt *(54) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt *(55) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/ila_v6_2/doc/ila_v6_2_changelog.txt *(56) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_switchboard_v1_0/doc/sc_switchboard_v1_0_changelog.txt *(57) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_switchboard_v1_0/doc/sc_switchboard_v1_0_changelog.txt *(58) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_switchboard_v1_0/doc/sc_switchboard_v1_0_changelog.txt *(59) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(60) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(61) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(62) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_exit_v1_0/doc/sc_exit_v1_0_changelog.txt *(63) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(64) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_sc2axi_v1_0/doc/sc_sc2axi_v1_0_changelog.txt *(65) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(66) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/xlconstant_v1_1/doc/xlconstant_v1_1_changelog.txt *(67) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(68) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_switchboard_v1_0/doc/sc_switchboard_v1_0_changelog.txt *(69) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_axi2sc_v1_0/doc/sc_axi2sc_v1_0_changelog.txt *(70) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_mmu_v1_0/doc/sc_mmu_v1_0_changelog.txt *(71) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_si_converter_v1_0/doc/sc_si_converter_v1_0_changelog.txt *(72) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_transaction_regulator_v1_0/doc/sc_transaction_regulator_v1_0_changelog.txt *(73) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_axi2sc_v1_0/doc/sc_axi2sc_v1_0_changelog.txt *(74) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_mmu_v1_0/doc/sc_mmu_v1_0_changelog.txt *(75) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_si_converter_v1_0/doc/sc_si_converter_v1_0_changelog.txt *(76) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_transaction_regulator_v1_0/doc/sc_transaction_regulator_v1_0_changelog.txt *(77) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(78) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(79) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(80) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(81) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(82) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(83) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(84) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(85) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(86) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(87) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_switchboard_v1_0/doc/sc_switchboard_v1_0_changelog.txt *(88) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_exit_v1_0/doc/sc_exit_v1_0_changelog.txt *(89) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_sc2axi_v1_0/doc/sc_sc2axi_v1_0_changelog.txt *(90) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/xlconstant_v1_1/doc/xlconstant_v1_1_changelog.txt *(91) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(92) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_axi2sc_v1_0/doc/sc_axi2sc_v1_0_changelog.txt *(93) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_mmu_v1_0/doc/sc_mmu_v1_0_changelog.txt *(94) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_si_converter_v1_0/doc/sc_si_converter_v1_0_changelog.txt *(95) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_transaction_regulator_v1_0/doc/sc_transaction_regulator_v1_0_changelog.txt *(96) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(97) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_node_v1_0/doc/sc_node_v1_0_changelog.txt *(98) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_exit_v1_0/doc/sc_exit_v1_0_changelog.txt *(99) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_sc2axi_v1_0/doc/sc_sc2axi_v1_0_changelog.txt *(100) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/xlconstant_v1_1/doc/xlconstant_v1_1_changelog.txt *(101) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt *(102) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_axi2sc_v1_0/doc/sc_axi2sc_v1_0_changelog.txt *(103) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_mmu_v1_0/doc/sc_mmu_v1_0_changelog.txt *(104) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_si_converter_v1_0/doc/sc_si_converter_v1_0_changelog.txt *(105) c:/Xilinx/Vivado/2023.1/data/ip/xilinx/sc_transaction_regulator_v1_0/doc/sc_transaction_regulator_v1_0_changelog.txt *(106) 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Hi @artvvb, updated the top design wrapper, now getting "[Synth 8-439] module 'design_1_create_tlast_0_0' not found" for a few IP's. I've tried adding IP from sources a few times and installed y2k22_patch, which pops up as a reason for this in earlier versions. Thanks for any input. Probably something stupid I did along the way. Seems to be an infinite number of ways to make this process difficult! WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Implementation target. Since these IPs are locked, no update to the output products can be done. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. C:/Users/LENOVO/Documents/GitHub/hw/hw.srcs/sources_1/bd/design_1/design_1.bd [Wed Dec 27 11:18:21 2023] Launched design_1_processing_system7_0_0_synth_1, design_1_c_accum_1_0_synth_1, design_1_c_accum_0_2_synth_1, design_1_axi_fifo_mm_s_0_0_synth_1, design_1_axis_register_slice_0_1_synth_1, design_1_extend_pulse_0_0_synth_1, design_1_create_tlast_0_0_synth_1... Run output will be captured here: design_1_processing_system7_0_0_synth_1: C:/Users/LENOVO/Documents/GitHub/hw/hw.runs/design_1_processing_system7_0_0_synth_1/runme.log design_1_c_accum_1_0_synth_1: C:/Users/LENOVO/Documents/GitHub/hw/hw.runs/design_1_c_accum_1_0_synth_1/runme.log design_1_c_accum_0_2_synth_1: C:/Users/LENOVO/Documents/GitHub/hw/hw.runs/design_1_c_accum_0_2_synth_1/runme.log design_1_axi_fifo_mm_s_0_0_synth_1: C:/Users/LENOVO/Documents/GitHub/hw/hw.runs/design_1_axi_fifo_mm_s_0_0_synth_1/runme.log design_1_axis_register_slice_0_1_synth_1: C:/Users/LENOVO/Documents/GitHub/hw/hw.runs/design_1_axis_register_slice_0_1_synth_1/runme.log design_1_extend_pulse_0_0_synth_1: C:/Users/LENOVO/Documents/GitHub/hw/hw.runs/design_1_extend_pulse_0_0_synth_1/runme.log design_1_create_tlast_0_0_synth_1: C:/Users/LENOVO/Documents/GitHub/hw/hw.runs/design_1_create_tlast_0_0_synth_1/runme.log [Wed Dec 27 11:18:23 2023] Launched synth_1...

See this response, I didn't change any port definitions from the baseline DDR project though, I think mine has more to do with the AXI stream perhaps, let me know....

@artvvb, Realize its the holidays, throwing this out whenever you can have a look or anyone else following. I"m still trying to diagnose. Synthesis and implementation pass. Quite a few ip upgrade errors. Bitstream failed to generate, Thanks, ERROR: [DRC NSTD-1] Unspecified I/O Standard: 171 out of 171 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: beat_count[31:0], error_count[31:0], m_tdata[31:0], miss_count[31:0], s_tdata[31:0], clk, decouple_streams, idle, m_tlast, m_tready, m_tvalid, resetn, s_tlast, s_tready, s_tvalid... and (the first 15 of 16 listed). ERROR: [DRC UCIO-1] Unconstrained Logical Port: 171 out of 171 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: beat_count[31:0], error_count[31:0], m_tdata[31:0], miss_count[31:0], s_tdata[31:0], clk, decouple_streams, idle, m_tlast, m_tready, m_tvalid, resetn, s_tlast, s_tready, s_tvalid... and (the first 15 of 16 listed). WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [Vivado 12-3199] DRC finished with 2 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. INFO: [Common 17-83] Releasing license: Implementation 19 Infos, 2 Warnings, 0 Critical Warnings and 3 Errors encountered. write_bitstream failed ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors. INFO: [Common 17-206] Exiting Vivado at Tue Dec 26 12:21:30 2023... [DRC NSTD-1] Unspecified I/O Standard: 171 out of 171 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: beat_count[31:0], error_count[31:0], m_tdata[31:0], miss_count[31:0], s_tdata[31:0], clk, decouple_streams, idle, m_tlast, m_tready, m_tvalid, resetn, s_tlast, s_tready, s_tvalid... and (the first 15 of 16 listed).