Waveforms - Digital Discovery - Detect falling edge of DIO. Drive another DIO low for Y cycles, X clock cycles later

[Mike4354]

Detect falling edge of DIO.  Drive another DIO low for Y cycles, X clock cycles later.

For reference I am using the Waveforms software in conjunction with the Digital Discovery.

I would like to perform the following using the digital pattern generator.  Set up a DIO as an input and detect a falling edge on this signal.  Once this falling edge is detected, I would like to drive another DIO low for Y clock cycles, X clock cycles later.  This is depicted below.

I couldn't figure out a way to set this up in hardware using the settings in the Waveforms software.  Started going down the path of setting this up on the ROM logic, basically making a truth table to enter into the state machine when DIO 1 goes low and create X states using a binary counter that would result in still holding DIO 2 HIGH, followed by Y states using a binary counter that would result in holding DIO 2 LOW, then set it HIGH again until the next falling edge of DIO 1.

I did use the SDK to try to achieve the same result, but running this logic through software seems much too slow.  Would like a response within 100 to 200 ns if possible.  Is this realistic?

I'm hoping there is a simpler solution to this, so wanted to ask if there was an easier way to achieve this goal before heading down this path.

Edited April 26 by Mike4354
Clarification of HW/SW Used

[attila]

Hi @Mike4354

Here the Logic Analyzer detector is set to trigger on DIO 24 falling edge and Pattern Generator outputs a 100ns low pulse on DIO 25 with 200ns (20 cycles @ 100MHz) + Wait time delay.

 

You could adjust the system frequency to change the delay, 250ns (20 @ 80MHz) +

 

With ROM logic the delay is lower, 80ns at 100MHz (DIO 26 is used as state bit)

 

Reducing the ROM frequency will result in delay uncertainty, but delay could be achieved with further state bits.

 

[Mike4354]

Hi @attila, thank you for the reply.  This is a great start.  I now understand that we can use the "Run" period of the pattern generator to control the period of time the pattern generator will generate a pattern for i.e. the Y clock cycles in the original question.

It doesn't really seem like controlling the frequency of the logic analyzer is a reliable way to control the delay before the pattern starts.  There's also very little granularity in terms of what delay can be specified.  Based on what you're saying, running the logic analyzer at 100 MHz and adding multiple state variables to add the delay seems like the best option.

Is adding a configurable delay between a trigger event and an action on a pin realistic for a future improvement?

And just to be clear with the request, can you confirm if there is any way to add an arbitrary delay on the signal in the current Waveforms software without needing to add an additional row in the ROM Logic table for every delay step that needs to be added.

 

Edited April 29 by Mike4354
Further clarification on my request

[Mike4354]

@attila What ended up working really well for me in terms of being able to control the delay for when the pattern started is actually the "Wait" parameter in the pattern generator, whereas using the "Run" parameter as you mentioned above worked really well for controlling the width.

Thanks for all of your help, it is greatly appreciated!

[attila]

Hi @Mike4354

Currently the Pattern output delay from Logic Detector trigger is 200ns + the specified Wait time.
The next version, hopefully tomorrow, will allow any DIN/DIO to be used directly as trigger source, reducing the minimum delay to 120ns

[attila]

Hi @Mike4354

The minimum Pattern delay from DIO or DIN trigger source is 12 cycles, 120ns at 100MHz or with overclocking to 120MHz will be ~100ns.

[Mike4354]

@attila That is a fantastic feature, just tested it and it works well!

Edited April 30 by Mike4354
grammatical error

[Mike4354]

@attila Would it be in the realm of possibility to be able to run more than 1 pattern generator at a time?  If not, is there any way to make different signals in a single pattern generator have different durations.  The screenshot below shows 2 different patterns that I would like to run for different durations.  Both are triggered off the falling edge of the same signal, but there "Run" time needs to be different.

If there is not a direct way to achieve this result, is there some sort of workaround or alternative method that you can think of?

[attila]

Hi @Mike4354

Use Pulse, Idle: High Start:Low

[Mike4354]

@attila Thanks, that makes sense.  So is there any way to use 2 different pattern generators or 2 different conditions to trigger the pattern generator?  For example, instead of just the falling edge of DIO28, it could be the falling edge of DIO28 AND DIO 29 is HIGH, or something like that.

[Mike4354]

@attila Wanted to sneak in one more question closely related to the above.  Are the selections for the run period and wait period arbitrarily limited to specific dropdown menu items below, and if so, can this possibly be expanded?  For example, I need the binary counter to run for a few different periods between 1 and 2 microseconds and then go back into Hi-Z state, as I am operating on a multiplexed bus.  It would be nice to be able to run at 1 us, 1.1 us, 1.2 us, 1.5 us, etc.  Even more granularity would be nice.

I'm sure more expensive logic analyzers could do this, but if the Digital Discovery can achieve this, that would be huge.

Edited Thursday at 06:00 PM by Mike4354
Clarifying Question

[attila]

Hi @Mike4354

All editable input fields in the application accept typing in custom values. The presets are just example/convenience values.
Run and wait have system clock resolution, 10ns at 100MHz, up to 2^43 cycles, maximum rounded in the interface to 24hr. This also limits the number of displayed digits.

[Mike4354]

@attila Understood, thank you for the insight!  That worked well.