DIO selection limitation with I2C, SWD

[jostikas]

Hi!

Waveforms 3.22.2, AD3

Protocol.I2C.SCL.text = "DIO 14"
Protocol.I2C.SDA.value = PIN_TEST_SDA;

Expected: SCL set to DIO 14

Actual: SCL set to DIO 10

I can't set Protocol.I2C clock or data pins to values (or texts) above DIO10 (DIO9 on AD2). For that matter, with SWD it only goes up to DIO 9.

Is this a hardware limitation? Is there any workaround? Where might such limitations be documented?
I'm bringing up a custom "functional tester" board, that implements the pinout of the AD2/3 connector... but the on-board IO expansion is on pins 7 and 14 (because that made routing make more sense, and because I didn't know there were limitations)

EDIT: Also confirmed on 3.22.18

Edited April 12 by jostikas

[attila]

Hi @jostikas

The I2C master (with clock stretching) and slave mode is implemented using state machine, 'ROM logic' feature of Pattern Generator.
Since both the clock and data lines are inputs for machine, these need to use the least significant bits, up to the log2 of Patterns device buffer size.
The default configuration for AD3 allocates 2k samples for Patterns so DIO 0 to 10 can be used.
With the 5th configuration 32k samples and DIO 0 to 15 can be used for I2C.

The no clock stretching implementation is not recommended since it simply generates clock/data pattern, is is kept for backward compatibility, since this was the first implementation.

[JColvin]

Hi @jostikas,

I suspect that this is a software bug rather than a hardware one (I verified your experience was also present on the 3.16.3 release) since, as far as I understand, all DIO pins for both the Analog Discovery 2/3 are implemented identically on the PCB side of things.

Regardless, thank you for bringing this up since I do not recall anybody mentioning this before on the Forum or otherwise.

I'm not personally don't have any further information, but am hoping that Attila will have some further insight when it's no longer the weekend in his timezone.

Thanks,
JColvin

[jostikas]

Thank you, both, for a quick answer.

While I could manage without clock streching on that bus, I need it on the other that I switch to (that would be within allowed range), and I would prefer more analog buffer. To avoid future mistakes, I'll probably bodge the 5 rev1 PCBs to match rev2, instead of software workarounds.

If I may suggest, the title of this thread could be changed to something like "DIO selection limitation with I2C, SWD" to make it better searchable for future people.

[attila]

Hi @jostikas

I added information to the Help.