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To implement an interface to fast speed communicate among multiple FPGAs(now we will use Zybo).


Tomohiro Yoshida

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In order to achieve that kind of speed between boards, you definitely need differential signaling, requiring two pins per signal.

How many pins do you have available for this? According to the datasheet, there are 3 "high speed" PMOD connectors, each supporting 4 differential pairs. Let's use 2 pair per PMOD for transmitting, and 2 for receiving.

The Zybo FPGA unfortunately does not have any GTP transceivers, so the speed per signal is limited to what the SERDES can deliver. ISERDES and OSERDES are documented here: http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

The ISERDES does support some level of oversampling, so possibly you can recover the clock from the data, but more likely you need to have a dedicated clock differential pair in the same connector as the transmit and receive signals.

If you keep clock skew very low, you can send two bits per clock cycle per differential pair.

This artix7 overview document says something about 1.25Gbps using the SERDES in Artix. If so, you just might be able to achieve 10Gb/s (adding together transmit and receive) with the pins available in Zybo.

It would be much simpler if you could use a zc015 (with GTP transceivers) rather than zc010 (only SERDES).

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Hi Tomohiro Yoshida,

Instead of the Zybo I, would suggest using the Genesis 2 which has multiple GTX transceivers at over 10 Gbs each. You would need 10G FMC cards with SFP cages to facilitate the connections which a quick google search should provide a few options. 

thank you,

Jon

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