ps7_init.tcl file seems to be incorrect?

[Dayrider10]

Hello!

This is my first post here and hopefully I don't break any forum rules! I am a software engineer by profession but I am starting to learn FPGAs.

I have an ArtyZ7-10 board. I have been trying these past couple of days to get a simple bare metal program to work. The program is a simple Hello World that is sent over the UART communication every 5 seconds. Below is my block design

 

It's a pretty simple block diagram using the ZYNQ7 PS. I have enabled UART1 as seen below (well also UART0 but ignoring that for now)

 

 

My code is below (using the example Hello World program)

/******************************************************************************
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*
 * helloworld.c: simple test application
 *
 * This application configures UART 16550 to baud rate 9600.
 * PS7 UART (Zynq) is not initialized by this application, since
 * bootrom/bsp configures it to baud rate 115200
 *
 * ------------------------------------------------
 * | UART TYPE   BAUD RATE                        |
 * ------------------------------------------------
 *   uartns550   9600
 *   uartlite    Configurable only in HW design
 *   ps7_uart    115200 (configured by bootrom/bsp)
 */

#include <stdio.h>
#include "sleep.h"
#include "platform.h"
#include "xil_printf.h"


int main()
{
    init_platform();

    // Please just keep printing out something. Or print anything at all please
    while (1) {
        printf("Hello World!\r\n");
        usleep(5000000);
    }

    cleanup_platform();
    return 0;
}

Now when I tested this why the Arty board connected up (the jumpers are on the JTAG and I am using an external 15v power supply), it programs the board correctly, but then nothing seems to happen. The RX led does not send anything. I downloaded the out of box demo code. I first switched out my design with that and it didn't work. I then switched out my generated ps7_init.tcl file with the out of box demo's ps7_init.tcl file and it worked. Using the same out of box ps7_init.tcl file, I switched back to my bitstream design and it still worked.

So I am having trouble understanding why the out of box ps7_init file would work but my generated one won't set up UART correctly. I have created a wrapper in my design and I did export it out to the XSA file and imported that correctly. Any time I make a change to the design (which really doesn't happen), I regenerate the wrapper and then re-export and then update the XSA reference in Vitis.

Does anyone have an idea of where I am going wrong? Again I am pretty new to the realm of FPGAs and hardware so I am sorry if I ask any dumb questions.

EDIT: I should also note that I do have my serial terminal set up correctly. I am using Tera Term. I can provide my ps7_init file upon request but I don't know how much help that would be.

Edited February 2 by Dayrider10
Adding more information

[Viktor Nikolov]

What is your motivation for enabling UART1?

The Arty Z7 reference manual says that USB-UART bridge is to be used with UART 0. It is wired to UART 0 Zynq IC pins.

How do your Board Support Package (BSP) settings look like in Vitis?

I attached a screenshot of the BSP settings of a functional Zynq project. stdin and stdout need to be configured to UART 0 because your HW design doesn't expose UART 1 pins to PL and output ports, and thus, you can't access UART 1 in any way.

Viktor

[Viktor Nikolov]

Just to add for clarity:

You configured UART 1 to use MIO pins 8 and 9. However, almost all MIO pins are connected to some peripherals on the Arty Z7 board itself (e.g., flash, Ethernet). See the table in this chapter of the Reference Manual and check what MIO pins 8 and 9 are connected to.

According to that table, UART 0 has to be configured on MIO pins 14 and 15!

If you want to use UART 1, you need to set it to use EMIO. Then, it would appear as a signal on the Zynq IP and could be routed to I/O ports

Edited February 2 by Viktor Nikolov

[Dayrider10]

Ahh ok that makes way more sense! Thank you! Let me try those changes out.

Initially I was thinking that I needed UART1 for STDIN (which believe it or not I did look at the BSP and it still didn't click to me lol), which when I say it out loud doesn't make too much sense.

Thank you for pointing me to the right place in the manuals. I've had them up but sometimes I find it hard to locate what I need. Again all still a learning process! Let me make those changes.

[JColvin]

Digilent also provides a board file preset that will correctly configure the Zynq block with its various on board peripherals, including UART, for you; https://digilent.com/reference/programmable-logic/guides/installing-vivado-and-vitis#install_digilent_s_board_files. When adding the Zynq block to the Block Design, you'll just need to check the Apply Board Preset box (visual in the Add a Zynq processor dropdown here: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi#add_a_processor_to_a_block_design).

Let me know if you have any questions.

Thanks,
JColvin